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ORCIDASYNC 1995: London, UK
- Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK. IEEE Computer Society 1995, ISBN 0-8186-7098-3
Pipelines
- David A. Kearney, Neil W. Bergmann:
Performance evaluation of asynchronous logic pipelines with data dependent processing delays. 4-13 - Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas:
New CMOS VLSI linear self-timed architectures. 14-23 - Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev:
Low-latency asynchronous FIFO buffers. 24-31 - Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov:
Designing an asynchronous pipeline token ring interface. 32-
Silicon Compilation I
- Joep L. W. Kessels:
VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player. 44-52 - Ad M. G. Peeters, Kees van Berkel:
Single-rail handshake circuits. 53-62 - Rik van de Wiel:
High-level test evaluation of asynchronous circuits. 63-71 - Kees van Berkel, Ronan Burgess, Joep L. W. Kessels, Ad M. G. Peeters, Marly Roncken, Frits D. Schalij, Rik van de Wiel:
A single-rail re-implementation of a DCC error detector using a generic standard-cell library. 72-
Silicon Compilation II
- Andrew M. Bailey, Mark B. Josephs:
Sequencer circuits for VLSI programming. 82-90 - Craig Farnsworth, David A. Edwards, Jianwei Liu, Shiv S. Sikand:
A hybrid asynchronous system design environment. 91-98 - Kees van Berkel, Ferry Huberts, Ad M. G. Peeters:
Stretching quasi delay insensitivity by means of extended isochronic forks. 99-
Synthesis/Verification
- Radu Negulescu, Janusz A. Brzozowski:
Relative liveness: from intuition to automated verification. 108-117 - Chantal Ykman-Couvreur, Bill Lin:
Optimised state assignment for asynchronous circuit synthesis. 118-127 - Oriol Roig, Jordi Cortadella
, Enric Pastor:
Hierarchical gate-level verification of speed-independent circuits. 128-137 - Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng:
Technology mapping of timed circuits. 138-
Testing; Completion-Detection
- Janusz A. Brzozowski, Kaamran Raahemifar:
Testing C-elements is not elementary. 150-159 - Ajay Khoche, Erik Brunvand:
Testing self-timed circuits using partial scan. 160-169 - Eckhard Grass, Simon Jones:
Asynchronous circuits based on multiple localised current-sensing completion detection. 170-
Microprocessors
- Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt:
ECSTAC: a fast asynchronous microprocessor. 180-189 - D. K. Arvind, Robert D. Mullins, Vinod E. F. Rebello:
Micronets: a model for decentralising control in asynchronous processor architectures. 190-199 - C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven:
Hades-towards the design of an asynchronous superscalar processor. 200-209 - Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu:
ARAS: asynchronous RISC architecture simulator. 210-
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