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2020 – today
- 2024
[e1]Kenji Kise, Valentina Salapura, Murali Annavaram, Ana Lucia Varbanescu:
Proceedings of the 38th ACM International Conference on Supercomputing, ICS 2024, Kyoto, Japan, June 4-7, 2024. ACM 2024 [contents]- 2023
- [j21]Fumio Hamanaka
, Takashi Odan, Kenji Kise, Thiem Van Chu:
An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration. IEEE Access 11: 5701-5713 (2023) - [c56]Md. Ashraful Islam, Kenji Kise:
Resource-efficient RISC-V Vector Extension Architecture for FPGA-based Accelerators. HEART 2023: 78-85 - [c55]Kenji Kise:
An open-source and GUI-capable RISC-V computer system on a low-end FPGA board. MCSoC 2023: 23-30 - [c54]Yuji Yamada, Nesrine Berjab, Tomohiro Yoneda, Kenji Kise:
A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs. MCSoC 2023: 31-37 - 2022
- [j20]Md. Ashraful Islam, Kenji Kise:
An Efficient Resource Shared RISC-V Multicore Architecture. IEICE Trans. Inf. Syst. 105-D(9): 1506-1515 (2022) - [j19]Takuto Kanamori, Takashi Odan, Kazuki Hirohata, Kenji Kise:
RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor. IEICE Trans. Inf. Syst. 105-D(12): 1999-2007 (2022) - 2021
- [c53]Takashi Odan, Takuto Kanamori, Kenji Kise:
A function-rich FPGA system of camera image processing for video meeting. MCSoC 2021: 31-37 - [c52]Takuto Kanamori, Kenji Kise:
RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions. MCSoC 2021: 38-45 - [c51]Fumio Hamanaka, Takuto Kanamori, Kenji Kise:
A Low Cost and Portable Mini Motor Car System with a BNN Accelerator on FPGA. MCSoC 2021: 84-91 - [c50]Md. Ashraful Islam, Kenji Kise:
Efficient Resource Shared RISC-V Multicore Processor. MCSoC 2021: 366-372 - 2020
- [j18]Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise:
RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining. IEICE Trans. Inf. Syst. 103-D(12): 2494-2503 (2020) - [j17]Elsayed A. Elsayed, Kenji Kise:
High-Performance and Hardware-Efficient Odd-Even Based Merge Sorter. IEICE Trans. Inf. Syst. 103-D(12): 2504-2517 (2020) - [c49]Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka:
Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs. FPGA 2020: 211-221 - [i4]Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise:
RVCoreP : An optimized RISC-V soft processor of five-stage pipelining. CoRR abs/2002.03568 (2020) - [i3]Junya Miura, Hiromu Miyazaki, Kenji Kise:
A portable and Linux capable RISC-V computer system in Verilog HDL. CoRR abs/2002.03576 (2020) - [i2]Md. Ashraful Islam, Hiromu Miyazaki, Kenji Kise:
RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors. CoRR abs/2010.16171 (2020) - [i1]Takuto Kanamori, Hiromu Miyazaki, Kenji Kise:
RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions. CoRR abs/2011.11246 (2020)
2010 – 2019
- 2019
- [j16]Thiem Van Chu, Kenji Kise:
LEF: An Effective Routing Algorithm for Two-Dimensional Meshes. IEICE Trans. Inf. Syst. 102-D(10): 1925-1941 (2019) - [c48]Hiromu Miyazaki, Junya Miura, Kenji Kise:
An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA. HEART 2019: 14:1-14:4 - [c47]Katsunoshin Matsui, Md. Ashraful Islam, Kenji Kise:
An Efficient Implementation of a TAGE Branch Predictor for Soft Processors on FPGA. MCSoC 2019: 108-115 - [c46]Elsayed A. Elsayed, Kenji Kise:
Towards an Efficient Hardware Architecture for Odd-Even Based Merge Sorter. MCSoC 2019: 249-256 - 2018
- [j15]Shimpei Sato, Ryohei Kobayashi, Kenji Kise:
ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment. IEICE Trans. Inf. Syst. 101-D(2): 344-353 (2018) - [c45]Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise:
A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath. FCCM 2018: 197-204 - [c44]Thiem Van Chu, Kenji Kise:
An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs. FPL 2018: 419-426 - [c43]Makoto Saitoh, Kenji Kise:
Very Massive Hardware Merge Sorter. FPT 2018: 86-93 - [c42]Kenji Kise:
Swap Based Merge Network for High Performance Sorting Accelerators. HEART 2018: 8:1-8:7 - [c41]Yuuma Azuma, Hayato Sakagami, Kenji Kise:
An Efficient Parallel Hardware Scheme for Solving the N-Queens Problem. MCSoC 2018: 16-22 - [c40]Elsayed A. Elsayed, Kenji Kise:
Design and Evaluation of a Configurable Hardware Merge Sorter for Various Output Records. MCSoC 2018: 201-208 - 2017
- [j14]Ryohei Kobayashi, Kenji Kise:
A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism. IEICE Trans. Inf. Syst. 100-D(5): 1003-1015 (2017) - [j13]Thiem Van Chu, Shimpei Sato, Kenji Kise:
Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA. ACM Trans. Reconfigurable Technol. Syst. 10(4): 27:1-27:27 (2017) - [c39]Susumu Mashimo, Thiem Van Chu, Kenji Kise:
High-Performance Hardware Merge Sorter. FCCM 2017: 1-8 - [c38]Thiem Van Chu, Myeonggu Kang, Shi Fa, Kenji Kise:
Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip. MCSoC 2017: 83-90 - 2016
- [j12]Susumu Mashimo, Thiem Van Chu, Kenji Kise:
Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator. SIGARCH Comput. Archit. News 44(4): 8-13 (2016) - [j11]Ryohei Kobayashi, Tomohiro Misono, Kenji Kise:
A High-speed Verilog HDL Simulation Method using a Lightweight Translator. SIGARCH Comput. Archit. News 44(4): 26-31 (2016) - [c37]Takuma Usui, Thiem Van Chu, Kenji Kise:
A Cost-Effective and Scalable Merge Sorter Tree on FPGAs. CANDAR 2016: 47-56 - [c36]Eri Ogawa, Kenji Kise:
An Effective Page Padding Method for RAM Buffer Algorithms to Enhance the SSD Endurance. CANDAR 2016: 133-139 - [c35]Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda:
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. NOCS 2016: 1-8 - 2015
- [j10]Shinya Takamaeda-Yamazaki, Hiroshi Nakatsuka, Yuichiro Tanaka, Kenji Kise:
Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs. IEICE Trans. Inf. Syst. 98-D(12): 2150-2158 (2015) - [c34]Shimpei Sato, Kenji Kise:
ArchHDL: A Novel Hardware RTL Design Environment in C++. ARC 2015: 53-64 - [c33]Takuma Usui, Ryohei Kobayashi, Kenji Kise:
A Challenge of Portable and High-Speed FPGA Accelerator. ARC 2015: 383-392 - [c32]Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise:
Dependable real-time task execution scheme for a many-core platform. DFTS 2015: 197-204 - [c31]Thiem Van Chu, Shimpei Sato, Kenji Kise:
Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA. FCCM 2015: 60-63 - [c30]Thiem Van Chu, Shimpei Sato, Kenji Kise:
Ultra-fast NoC emulation on a single FPGA. FPL 2015: 1-8 - [c29]Yuki Matsuda, Ryosuke Sasakawa, Kenji Kise:
A Challenge for an Efficient AMI-based Cache System on FPGA Soft Processors. CANDAR 2015: 133-139 - [c28]Tomohiro Misono, Ryohei Kobayashi, Shimpei Sato, Kenji Kise:
Effective Parallel Simulation of ArchHDL under Manycore Environment. CANDAR 2015: 140-146 - [c27]Ryohei Kobayashi, Kenji Kise:
FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems. MCSoC 2015: 49-56 - [c26]Eri Ogawa, Yuki Matsuda, Tomohiro Misono, Ryohei Kobayashi, Kenji Kise:
Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research. MCSoC 2015: 65-72 - 2014
- [c25]Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura:
An NoC-based evaluation platform for safety-critical automotive applications. APCCAS 2014: 679-682 - [c24]Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise:
Ultrasmall: The smallest MIPS soft processor. FPL 2014: 1-4 - [c23]Shinya Takamaeda-Yamazaki, Kenji Kise:
flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms. FPL 2014: 1-4 - [c22]Haruka Mori, Kenji Kise:
Design and Performance Evaluation of a Manycore Processor for Large FPGA. MCSoC 2014: 207-214 - [c21]Thiem Van Chu, Shimpei Sato, Kenji Kise:
KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs. MCSoC 2014: 215-222 - [c20]Shinya Takamaeda-Yamazaki, Kenji Kise:
A framework for efficient rapid prototyping by virtually enlarging FPGA resources. ReConFig 2014: 1-8 - 2013
- [j9]Yuichiro Tanaka, Shimpei Sato, Kenji Kise:
The Ultrasmall soft processor. SIGARCH Comput. Archit. News 41(5): 95-100 (2013) - [c19]Takakazu Ikeda, Kenji Kise:
Application Aware DRAM Bank Partitioning in CMP. ICPADS 2013: 349-356 - [c18]Ryosuke Sasakawa, Kenji Kise:
LEF: long edge first routing for two-dimensional mesh network on chip. NoCArc@MICRO 2013: 5-10 - 2012
- [c17]Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise:
ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. ARC 2012: 138-150 - [c16]Tomoyuki Nagatsuka, Yoshito Sakaguchi, Kenji Kise:
CoreSymphony architecture. Conf. Computing Frontiers 2012: 249-252 - [c15]Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise:
Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations. ICNC 2012: 343-349 - 2011
- [j8]Tomoyuki Nagatsuka, Yoshito Sakaguchi, Takayuki Matsumura, Kenji Kise:
CoreSymphony: an efficient reconfigurable multi-core architecture. SIGARCH Comput. Archit. News 39(4): 32-37 (2011) - [j7]Shinya Takamaeda-Yamazaki, Ryosuke Sasakawa, Yoshito Sakaguchi, Kenji Kise:
An FPGA-based scalable simulation accelerator for tile architectures. SIGARCH Comput. Archit. News 39(4): 38-43 (2011) - [c14]Naoki Fujieda, Kenji Kise:
A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors. ICNC 2011: 160-165 - [c13]Mochamad Asri, Naoki Fujieda, Kenji Kise:
Rethinking processor instruction fetch: Inefficiencies-cracking mechanism. ISOCC 2011: 207-210 - 2010
- [c12]Takefumi Miyoshi, Kenji Kise, Hidetsugu Irie, Tsutomu Yoshinaga:
CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution. ICNC 2010: 71-77 - [c11]Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, Kenji Kise:
Smart Core System for Dependable Many-Core Processor with Multifunction Routers. ICNC 2010: 133-139 - [c10]Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, Kenji Kise:
Pattern-Based Systematic Task Mapping for Many-Core Processors. ICNC 2010: 173-178
2000 – 2009
- 2009
- [j6]Shimpei Sato, Naoki Fujieda, Akira Moriya, Kenji Kise:
SimCell: A Processor Simulator for Multi-Core Architecture Research. Inf. Media Technol. 4(2): 270-281 (2009) - [c9]Koh Uehara, Shimpei Sato, Takefumi Miyoshi, Kenji Kise:
A Study of an Infrastructure for Research and Development of Many-Core Processors. PDCAT 2009: 414-419 - [c8]Yosuke Mori, Kenji Kise:
The Cache-Core Architecture to Enhance the Memory Performance on Multi-Core Processors. PDCAT 2009: 445-450 - 2007
- [j5]Kenji Kise, Toshinori Sato, Hironori Nakajo:
Introduction. SIGARCH Comput. Archit. News 35(5): 1-2 (2007) - 2006
- [j4]Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba:
ABCLibScript: a directive to support specification of an auto-tuning facility for numerical software. Parallel Comput. 32(1): 92-112 (2006) - [j3]Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba:
ABCLib_DRSSED: A parallel eigensolver with an auto-tuning facility. Parallel Comput. 32(3): 231-250 (2006) - [c7]Satoshi Ohshima, Kenji Kise, Takahiro Katagiri, Toshitsugu Yuba:
Parallel Processing of Matrix Multiplication in a CPU and GPU Heterogeneous Environment. VECPAR 2006: 305-318 - 2005
- [j2]Sanya Tangpongprasit, Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba:
A time-to-live based reservation algorithm on fully decentralized resource discovery in Grid computing. Parallel Comput. 31(6): 529-543 (2005) - [c6]Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba:
Evaluation of the Acknowledgment Reduction in a Software-DSM System. PPAM 2005: 17-25 - 2004
- [c5]Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba:
Effect of auto-tuning with user's knowledge for numerical software. Conf. Computing Frontiers 2004: 12-25 - [c4]Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba:
The SimCore/Alpha Functional Simulator. WCAE 2004: 24 - 2003
- [c3]Kenji Kise, Hiroki Honda, Toshitsugu Yuba:
SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator. Asia-Pacific Computer Systems Architecture Conference 2003: 122-136 - [c2]Takahiro Katagiri, Kenji Kise, Hiroaki Honda, Toshitsugu Yuba:
FIBER: A Generalized Framework for Auto-tuning Software. ISHPC 2003: 146-159 - 2002
- [c1]Ryo Takata, Kenji Kise, Hiroki Honda, Toshitsugu Yuba:
DEM-1: A Particle Simulation Machine for Efficient Short-Range Interaction Computations. IPDPS 2002
1990 – 1999
- 1996
- [j1]Toshihiro Kato, Tomio Hirata, Toyofumi Saito, Kenji Kise:
An efficient algorithm for the euclidean distance transformation. Syst. Comput. Jpn. 27(7): 18-24 (1996)
Coauthor Index
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last updated on 2024-10-15 20:44 CEST by the dblp team
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