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ORCIDNatesan Venkateswaran
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2010 – 2019
- 2016
[c11]Tsung-Wei Huang, Martin D. F. Wong
, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran:
A distributed timing analysis framework for large designs. DAC 2016: 116:1-116:6- [c10]Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma:
Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. VLSID 2016: 493-498 - 2012
- [c9]Vladimir Zolotov, Debjit Sinha, Jeffrey G. Hemmett, Eric A. Foreman, Chandu Visweswariah, Jinjun Xiong, Jeremy Leitzen, Natesan Venkateswaran:
Timing analysis with nonseparable statistical and deterministic variations. DAC 2012: 1061-1066 - [c8]Debjit Sinha, Chandu Visweswariah, Natesan Venkateswaran, Jinjun Xiong, Vladimir Zolotov:
Reversible statistical max/min operation: concept and applications to timing. DAC 2012: 1067-1073
2000 – 2009
- 2006
- [j1]Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, Jeff Piaget, Natesan Venkateswaran, Jeffrey G. Hemmett:
First-Order Incremental Block-Based Statistical Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2170-2180 (2006) - [c7]Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah:
Criticality computation in parameterized statistical timing. DAC 2006: 63-68 - 2005
- [c6]Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown:
Optimization objectives and models of variation for statistical gate sizing. ACM Great Lakes Symposium on VLSI 2005: 313-316 - [c5]Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov:
Gate sizing using incremental parameterized statistical timing analysis. ICCAD 2005: 1029-1036
1990 – 1999
- 1999
- [c4]Kanad Chakraborty, Natesan Venkateswaran:
Congestion Mitigation During Placement. Great Lakes Symposium on VLSI 1999: 228-229 - 1998
- [c3]Natesan Venkateswaran, Dinesh Bhatia:
Clock-skew constrained placement for row based designs. ICCD 1998: 219-220 - 1997
- [c2]Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri:
A constructive method for data path area estimation during high-level VLSI synthesis. ASP-DAC 1997: 509-515 - 1996
- [c1]Natesan Venkateswaran, Dinesh Bhatia:
Clock-Skew Constrained Cell Placement. VLSI Design 1996: 146-149
Coauthor Index
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