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2020 – today
- 2022
[c15]Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen:
Flexible chip placement via reinforcement learning: late breaking results. DAC 2022: 1392-1393- [i1]Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen:
Flexible Multiple-Objective Reinforcement Learning for Chip Placement. CoRR abs/2204.06407 (2022) - 2020
- [c14]Tai-Chen Chen, Pei-Yu Lee, Tung-Chieh Chen:
Automatic Floorplanning for AI SoCs. VLSI-DAT 2020: 1-2
2010 – 2019
- 2014
- [c13]Chia-Yi Lee, Tai-Hung Li, Tai-Chen Chen:
Design-for-debug routing for FIB probing. DATE 2014: 1-4 - [c12]Iris Hui-Ru Jiang, Natarajan Viswanathan, Tai-Chen Chen, Jin-Fu Li:
The overview of 2014 CAD contest at ICCAD. ICCAD 2014: 356 - 2013
- [c11]Yu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Jimmy Liu, Tai-Chen Chen:
LASER: layout-aware analog synthesis environment on laker. ACM Great Lakes Symposium on VLSI 2013: 107-112 - [c10]Yun-Chih Tsai, Tai-Hung Li, Tai-Chen Chen, Chung-Wei Yeh:
Electromigration- and obstacle-avoiding routing tree construction. VLSI-DAT 2013: 1-4 - 2012
- [c9]Tai-Hung Li, Wan-Chun Chen, Xian-Ting Cai, Tai-Chen Chen:
Escape routing of differential pairs considering length matching. ASP-DAC 2012: 139-144 - [c8]Ta-Yu Kuan, Yi-Chun Chang, Tai-Chen Chen:
Micro-bump assignment for 3D ICs using order relation. ASP-DAC 2012: 341-346 - [c7]Bi-Ting Lai, Tai-Hung Li, Tai-Chen Chen:
Native-conflict-avoiding track routing for double patterning technology. SoCC 2012: 381-386 - 2011
- [c6]Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, Chien-Nan Jimmy Liu:
ILP-based inter-die routing for 3D ICs. ASP-DAC 2011: 330-335 - 2010
- [j3]Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang
:
Predictive Formulae for OPC With Applications to Lithography-Friendly Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 40-50 (2010)
2000 – 2009
- 2008
- [c5]Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang:
Predictive formulae for OPC with applications to lithography-friendly routing. DAC 2008: 510-515 - 2007
- [j2]Tai-Chen Chen, Yao-Wen Chang:
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1041-1053 (2007) - [c4]Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang:
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. ASP-DAC 2007: 238-243 - 2006
- [c3]Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin:
A novel framework for multilevel full-chip gridless routing. ASP-DAC 2006: 636-641 - 2005
- [c2]Tai-Chen Chen, Yao-Wen Chang:
Multilevel full-chip gridless routing considering optical proximity correction. ASP-DAC 2005: 1160-1163 - 2004
- [j1]Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang:
Timing modeling and optimization under the transmission line model. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 28-41 (2004) - 2001
- [c1]Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang:
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. ICCD 2001: 192-198
Coauthor Index
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