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2020 – today
- 2024
[c9]Hye Rim Ji, Jong Seong Kim, Jung Yun Choi, Jee Hyong Lee:
LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage. ASPDAC 2024: 484-490- 2023
- [j4]Seyoung Kim
, Seungho Yang, Hyein Lim, Hyein Lee, Jongwook Jeon, Jung Yun Choi, Jaeha Kim:
Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits. IEEE Access 11: 70691-70697 (2023) - 2021
- [c8]Hyojin Choi, In Huh, Seungju Kim, Jeonghoon Ko, Changwook Jeong, Hyeonsik Son, Kiwon Kwon, Joonwan Chai, Younsik Park, Jaehoon Jeong, Daesin Kim, Jung Yun Choi:
Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs. DAC 2021: 523-528
2010 – 2019
- 2016
- [c7]Jongho Kim, Gunhee Lee, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyung Tae Do, Jung Yun Choi:
Adaptive delay monitoring for wide voltage-range operation. DATE 2016: 511-516 - [c6]Srihari Yechangunja, Raj Shekhar, Mohit Kumar, Nikhil Tripathi, Abhishek Mittal, Abhishek Ranjan, Jianfeng Liu, Minyoung Mo, Kyung Tae Do, Jung Yun Choi, SungHo Park:
Sequential analysis driven reset optimization to improve power, area and routability. DATE 2016: 551-554 - 2015
- [c5]Jianfeng Liu, Mi-Suk Hong, Kyung Tae Do, Jung Yun Choi, Jaehong Park, Mohit Kumar, Manish Kumar, Nikhil Tripathi, Abhishek Ranjan:
Clock domain crossing aware sequential clock gating. DATE 2015: 1-6 - [c4]Sungmin Bae, Hyung-Ock Kim, Jung Yun Choi, Jaehong Park:
Coarse-grained Structural Placement for a Synthesized Parallel Multiplier. ISPD 2015: 17-24 - 2013
- [c3]Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker, Subhasish Mitra:
Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics. CICC 2013: 1-4 - [c2]Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker:
Early-life-failure detection using SAT-based ATPG. ITC 2013: 1-10 - 2010
- [j3]Hyung-Ock Kim, Bong Hyun Lee, Jong-Tae Kim, Jung Yun Choi, Kyu-Myung Choi, Youngsoo Shin:
Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 505-509 (2010)
2000 – 2009
- 2007
- [j2]Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi:
Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 758-766 (2007) - [c1]Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi:
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. ASP-DAC 2007: 654-659 - 2001
- [j1]Jung Yun Choi, Young Hwan Kim, Kyoung-Rok Cho:
Backward Propagated Capacitance Model for Register Transfer Level Power Estimation. VLSI Design 12(2): 221-231 (2001)
Coauthor Index
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