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ORCIDXiaolin Xu 0001
徐啸林
Person information
- unicode name: 徐啸林
- affiliation: Northeastern University, Boston, MA, USA
- affiliation (2018 - 2020): University of Illinois Chicago, IL, USA
- affiliation (2016 - 2018): University of Florida Gainesville, FL, USA
- affiliation (PhD 2016): University of Massachusetts Amherst, MA, USA
Other persons with the same name
- Xiaolin Xu — disambiguation page
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2020 – today
- 2024
[c51]Nuntipat Narkthong
, Shijin Duan, Shaolei Ren, Xiaolin Xu:
MicroVSA: An Ultra-Lightweight Vector Symbolic Architecture-based Classifier Library for Always-On Inference on Tiny Microcontrollers. ASPLOS (2) 2024: 730-745- [c50]Ziyu Liu, Tong Zhou, Yukui Luo, Xiaolin Xu:
TBNet: A Neural Architectural Defense Framework Facilitating DNN Model Protection in Trusted Execution Environments. DAC 2024: 310:1-310:6 - [c49]Tong Zhou, Shaolei Ren, Xiaolin Xu:
ArchLock: Locking DNN Transferability at the Architecture Level with a Zero-Cost Binary Predictor. ICLR 2024 - [c48]Yukui Luo, Adnan Siraj Rakin, Deliang Fan, Xiaolin Xu:
DeepShuffle: A Lightweight Defense Framework against Adversarial Fault Injection Attacks on Deep Neural Networks in Multi-Tenant Cloud-FPGA. SP 2024: 3293-3310 - [c47]Cheng Gongye, Yukui Luo, Xiaolin Xu, Yunsi Fei:
Side-Channel-Assisted Reverse-Engineering of Encrypted DNN Hardware Accelerator IP and Attack Surface Exploration. SP 2024: 4678-4695 - [c46]Nuntipat Narkthong, Chattriya Jariyavajee, Xiaolin Xu:
ALLI/O Diagram: An Action-based Visual Programming Language for Embedded System. VL/HCC 2024: 211-216 - [i29]Yejia Liu, Shijin Duan, Xiaolin Xu, Shaolei Ren:
Scheduled Knowledge Acquisition on Lightweight Vector Symbolic Architectures for Brain-Computer Interfaces. CoRR abs/2403.13844 (2024) - [i28]Ziyu Liu, Tong Zhou, Yukui Luo, Xiaolin Xu:
TBNet: A Neural Architectural Defense Framework Facilitating DNN Model Protection in Trusted Execution Environments. CoRR abs/2405.03974 (2024) - [i27]Tong Zhou, Xuandong Zhao, Xiaolin Xu, Shaolei Ren:
Bileve: Securing Text Provenance in Large Language Models Against Spoofing with Bi-level Signature. CoRR abs/2406.01946 (2024) - [i26]Shijin Duan, Chenghong Wang, Hongwu Peng, Yukui Luo, Wujie Wen, Caiwen Ding, Xiaolin Xu:
SSNet: A Lightweight Multi-Party Computation Scheme for Practical Privacy-Preserving Machine Learning Service in the Cloud. CoRR abs/2406.02629 (2024) - [i25]Tong Zhou, Jiahui Zhao, Yukui Luo, Xi Xie, Wujie Wen, Caiwen Ding, Xiaolin Xu:
AdaPI: Facilitating DNN Model Adaptivity for Efficient Private Inference in Edge Computing. CoRR abs/2407.05633 (2024) - 2023
- [c45]Cheng Gongye, Yukui Luo, Xiaolin Xu, Yunsi Fei:
HammerDodger: A Lightweight Defense Framework against RowHammer Attack on DNNs. DAC 2023: 1-6 - [c44]Hongwu Peng, Shanglin Zhou, Yukui Luo, Nuo Xu, Shijin Duan, Ran Ran, Jiahui Zhao, Chenghong Wang, Tong Geng, Wujie Wen, Xiaolin Xu, Caiwen Ding:
PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment. DAC 2023: 1-6 - [c43]Ziyu Liu, Yukui Luo, Shijin Duan, Tong Zhou, Xiaolin Xu:
MirrorNet: A TEE-Friendly Framework for Secure On-Device DNN Inference. ICCAD 2023: 1-9 - [c42]Ruyi Ding, Shijin Duan, Xiaolin Xu, Yunsi Fei:
VertexSerum: Poisoning Graph Neural Networks for Link Inference. ICCV 2023: 4509-4518 - [c41]Hongwu Peng, Shaoyi Huang, Tong Zhou, Yukui Luo, Chenghong Wang, Zigeng Wang, Jiahui Zhao, Xi Xie, Ang Li, Tony Geng, Kaleel Mahmood, Wujie Wen, Xiaolin Xu, Caiwen Ding:
AutoReP: Automatic ReLU Replacement for Fast Private Network Inference. ICCV 2023: 5155-5165 - [c40]Ran Ran, Xinwei Luo, Wei Wang, Tao Liu, Gang Quan, Xiaolin Xu, Caiwen Ding, Wujie Wen:
SpENCNN: Orchestrating Encoding and Sparsity for Fast Homomorphically Encrypted Neural Network Inference. ICML 2023: 28718-28728 - [c39]Tong Zhou, Yukui Luo, Shaolei Ren, Xiaolin Xu:
NNSplitter: An Active Defense Solution for DNN Model via Automated Weight Obfuscation. ICML 2023: 42614-42624 - [c38]Fangfang Yang, Shijin Duan, Xiaolin Xu, Shaolei Ren:
Achieving Certified Robustness for Brain-Inspired Low-Dimensional Computing Classifiers. INFOCOM Workshops 2023: 1-6 - [c37]Yukui Luo, Nuo Xu, Hongwu Peng, Chenghong Wang, Shijin Duan, Kaleel Mahmood, Wujie Wen, Caiwen Ding, Xiaolin Xu:
AQ2PNN: Enabling Two-party Privacy-Preserving Deep Neural Network Inference with Adaptive Quantization. MICRO 2023: 628-640 - [c36]Hongwu Peng, Ran Ran, Yukui Luo, Jiahui Zhao, Shaoyi Huang, Kiran Thorat, Tong Geng, Chenghong Wang, Xiaolin Xu, Wujie Wen, Caiwen Ding:
LinGCN: Structural Linearized Graph Convolutional Network for Homomorphically Encrypted Inference. NeurIPS 2023 - [i24]Hongwu Peng, Shanglin Zhou, Yukui Luo, Nuo Xu, Shijin Duan, Ran Ran, Jiahui Zhao, Shaoyi Huang, Xi Xie, Chenghong Wang, Tong Geng, Wujie Wen, Xiaolin Xu, Caiwen Ding:
RRNet: Towards ReLU-Reduced Neural Network for Two-party Computation Based Private Inference. CoRR abs/2302.02292 (2023) - [i23]Yejia Liu, Shijin Duan, Xiaolin Xu, Shaolei Ren:
MetaLDC: Meta Learning of Low-Dimensional Computing Classifiers for Fast On-Device Adaption. CoRR abs/2302.12347 (2023) - [i22]Tong Zhou, Yukui Luo, Shaolei Ren, Xiaolin Xu:
NNSplitter: An Active Defense Solution to DNN Model via Automated Weight Obfuscation. CoRR abs/2305.00097 (2023) - [i21]Hongwu Peng, Shanglin Zhou, Yukui Luo, Nuo Xu, Shijin Duan, Ran Ran, Jiahui Zhao, Chenghong Wang, Tong Geng, Wujie Wen, Xiaolin Xu, Caiwen Ding:
PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment. CoRR abs/2306.15513 (2023) - [i20]Ruyi Ding, Shijin Duan, Xiaolin Xu, Yunsi Fei:
VertexSerum: Poisoning Graph Neural Networks for Link Inference. CoRR abs/2308.01469 (2023) - [i19]Hongwu Peng, Shaoyi Huang, Tong Zhou, Yukui Luo, Chenghong Wang, Zigeng Wang, Jiahui Zhao, Xi Xie, Ang Li, Tony Geng, Kaleel Mahmood, Wujie Wen, Xiaolin Xu, Caiwen Ding:
AutoReP: Automatic ReLU Replacement for Fast Private Network Inference. CoRR abs/2308.10134 (2023) - [i18]Hongwu Peng, Ran Ran, Yukui Luo, Jiahui Zhao, Shaoyi Huang, Kiran Thorat, Tong Geng, Chenghong Wang, Xiaolin Xu, Wujie Wen, Caiwen Ding:
LinGCN: Structural Linearized Graph Convolutional Network for Homomorphically Encrypted Inference. CoRR abs/2309.14331 (2023) - [i17]Ziyu Liu, Yukui Luo, Shijin Duan, Tong Zhou, Xiaolin Xu:
MirrorNet: A TEE-Friendly Framework for Secure On-device DNN Inference. CoRR abs/2311.09489 (2023) - 2022
- [j15]Yupeng Hu, Linjun Wu, Zhuojun Chen, Yun Huang, Xiaolin Xu, Keqin Li, Jiliang Zhang:
STT-MRAM-Based Reliable Weak PUF. IEEE Trans. Computers 71(7): 1564-1574 (2022) - [j14]Linjun Wu, Yupeng Hu, Kehuan Zhang, Wenjia Li, Xiaolin Xu, Wanli Chang:
FLAM-PUF: A Response-Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4433-4444 (2022) - [j13]Wenhao Wang, Guangyu Hu, Xiaolin Xu, Jiliang Zhang:
CRAlert: Hardware-Assisted Code Reuse Attack Detection. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1607-1611 (2022) - [j12]Yukui Luo, Shijin Duan, Xiaolin Xu:
FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA. ACM Trans. Design Autom. Electr. Syst. 27(3): 24:1-24:31 (2022) - [c35]Shijin Duan, Shaolei Ren, Xiaolin Xu:
HDLock: exploiting privileged encoding to protect hyperdimensional computing models against IP stealing. DAC 2022: 679-684 - [c34]Shijin Duan, Yejia Liu, Shaolei Ren, Xiaolin Xu:
LeHDC: learning-based hyperdimensional computing classifier. DAC 2022: 1111-1116 - [c33]Yukui Luo, Shijin Duan, Cheng Gongye, Yunsi Fei, Xiaolin Xu:
NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering. FCCM 2022: 1-9 - [c32]Yukui Luo, Yuheng Zhang, Shijin Duan, Xiaolin Xu:
An Integrity Checking Framework for AXI Protocol in Multi-tenant FPGA. FPGA 2022: 155 - [c31]Yukui Luo, Yuheng Zhang, Shijin Duan, Xiaolin Xu:
A Cautionary Note on Building Multi-tenant Cloud-FPGA as a Secure Infrastructure. FPT 2022: 1-6 - [c30]Tong Zhou, Shaolei Ren, Xiaolin Xu:
ObfuNAS: A Neural Architecture Search-Based DNN Obfuscation Approach. ICCAD 2022: 81:1-81:9 - [i16]Shijin Duan, Xiaolin Xu, Shaolei Ren:
A Brain-Inspired Low-Dimensional Computing Classifier for Inference on Tiny Devices. CoRR abs/2203.04894 (2022) - [i15]Shijin Duan, Yejia Liu, Shaolei Ren, Xiaolin Xu:
LeHDC: Learning-Based Hyperdimensional Computing Classifier. CoRR abs/2203.09680 (2022) - [i14]Shijin Duan, Shaolei Ren, Xiaolin Xu:
HDLock: Exploiting Privileged Encoding to Protect Hyperdimensional Computing Models against IP Stealing. CoRR abs/2203.09681 (2022) - [i13]Yukui Luo, Shijin Duan, Cheng Gongye, Yunsi Fei, Xiaolin Xu:
NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering. CoRR abs/2203.12046 (2022) - [i12]Tong Zhou, Shaolei Ren, Xiaolin Xu:
ObfuNAS: A Neural Architecture Search-based DNN Obfuscation Approach. CoRR abs/2208.08569 (2022) - 2021
- [c29]Yukui Luo, Cheng Gongye, Yunsi Fei, Xiaolin Xu:
DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA. DAC 2021: 295-300 - [c28]Ke Xia, Yukui Luo, Xiaolin Xu, Sheng Wei:
SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous Architecture. DAC 2021: 301-306 - [c27]Wenhao Wang, Yukui Luo, Xiaolin Xu:
Constructive Use of Process Variations: Reconfigurable and High-Resolution Delay-Line. DATE 2021: 392-395 - [c26]Shijin Duan, Wenhao Wang, Yukui Luo, Xiaolin Xu:
A Survey of Recent Attacks and Mitigation on FPGA Systems. ISVLSI 2021: 284-289 - [c25]Shijin Duan, Xiaolin Xu:
HDCOG: A Lightweight Hyperdimensional Computing Framework with Feature Extraction. NANOARCH 2021: 1-6 - [c24]Tong Zhou, Yuheng Zhang, Shijin Duan, Yukui Luo, Xiaolin Xu:
Deep Neural Network Security From a Hardware Perspective. NANOARCH 2021: 1-6 - [c23]Adnan Siraj Rakin, Yukui Luo, Xiaolin Xu, Deliang Fan:
Deep-Dup: An Adversarial Weight Duplication Attack Framework to Crush Deep Neural Network in Multi-Tenant FPGA. USENIX Security Symposium 2021: 1919-1936 - [i11]Yukui Luo, Cheng Gongye, Yunsi Fei, Xiaolin Xu:
DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA. CoRR abs/2105.09453 (2021) - 2020
- [j11]Yukui Luo, Wenhao Wang, Scott Best, Yanzhi Wang, Xiaolin Xu:
A High-Performance and Secure TRNG Based on Chaotic Cellular Automata Topology. IEEE Trans. Circuits Syst. 67-I(12): 4970-4983 (2020) - [j10]Bicky Shakya, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte:
CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020(1): 175-202 (2020) - [c22]Yukui Luo, Xiaolin Xu:
A Dynamic Frequency Scaling Framework Against Reliability and Security Issues in Multi-tenant FPGA. FCCM 2020: 210 - [c21]Yifan Gong, Zheng Zhan, Zhengang Li, Wei Niu, Xiaolong Ma, Wenhao Wang, Bin Ren, Caiwen Ding, Xue Lin, Xiaolin Xu, Yanzhi Wang:
A Privacy-Preserving-Oriented DNN Pruning and Mobile Acceleration Framework. ACM Great Lakes Symposium on VLSI 2020: 119-124 - [c20]Yukui Luo, Xiaolin Xu:
A Quantitative Defense Framework against Power Attacks on Multi-tenant FPGA. ICCAD 2020: 64:1-64:9 - [c19]Yukui Luo, Cheng Gongye, Shaolei Ren, Yunsi Fei, Xiaolin Xu:
Stealthy-Shutdown: Practical Remote Power Attacks in Multi - Tenant FPGAs. ICCD 2020: 545-552 - [c18]Xiaolin Xu, Jiliang Zhang:
Rethinking FPGA Security in the New Era of Artificial Intelligence. ISQED 2020: 46-51 - [i10]Zheng Zhan, Yifan Gong, Zhengang Li, Pu Zhao, Xiaolong Ma, Wei Niu, Xiaolin Xu, Bin Ren, Yanzhi Wang, Xue Lin:
A Privacy-Preserving DNN Pruning and Mobile Acceleration Framework. CoRR abs/2003.06513 (2020) - [i9]Adnan Siraj Rakin, Yukui Luo, Xiaolin Xu, Deliang Fan:
Deep-Dup: An Adversarial Weight Duplication Attack Framework to Crush Deep Neural Network in Multi-Tenant FPGA. CoRR abs/2011.03006 (2020) - [i8]Bicky Shakya, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte:
Defeating CAS-Unlock. IACR Cryptol. ePrint Arch. 2020: 324 (2020)
2010 – 2019
- 2019
- [j9]Xiaolin Xu, Fahim Rahman, Bicky Shakya, Apostol Vassilev, Domenic Forte, Mark M. Tehranipoor:
Electronics Supply Chain Integrity Enabled by Blockchain. ACM Trans. Design Autom. Electr. Syst. 24(3): 31:1-31:25 (2019) - [c17]Scott Best, Xiaolin Xu:
An All-Digital True Random Number Generator Based on Chaotic Cellular Automata Topology. ICCAD 2019: 1-8 - [c16]Yukui Luo, Xiaolin Xu:
HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-Wires. FPT 2019: 331-334 - [c15]Shuo Li, Xiaolin Xu, Wayne P. Burleson:
PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process Variations. ISVLSI 2019: 574-579 - [i7]Zimu Guo, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte:
EOP: An Encryption-Obfuscation Solution for Protecting PCBs Against Tampering and Reverse Engineering. CoRR abs/1904.09516 (2019) - 2018
- [j8]Sarah Amir, Bicky Shakya, Xiaolin Xu, Yier Jin, Swarup Bhunia, Mark M. Tehranipoor, Domenic Forte:
Development and Evaluation of Hardware Obfuscation Benchmarks. J. Hardw. Syst. Secur. 2(2): 142-161 (2018) - [j7]Shahrzad Keshavarz, Cunxi Yu, Samaneh Ghandali, Xiaolin Xu, Daniel E. Holcomb:
Survey on Applications of Formal Methods in Reverse Engineering and Intellectual Property Protection. J. Hardw. Syst. Secur. 2(3): 214-224 (2018) - [j6]Zimu Guo, Xiaolin Xu, Md. Tauhidur Rahman, Mark M. Tehranipoor, Domenic Forte:
SCARe: An SRAM-Based Countermeasure Against IC Recycling. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 744-755 (2018) - [j5]Xiaolin Xu, Shahrzad Keshavarz, Domenic Forte, Mark M. Tehranipoor, Daniel E. Holcomb:
Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2431-2442 (2018) - [c14]Jungmin Park, Xiaolin Xu, Yier Jin, Domenic Forte, Mark M. Tehranipoor:
Power-based side-channel instruction-level disassembler. DAC 2018: 119:1-119:6 - [i6]Yansong Gao, Chenglu Jin, Jeeson Kim, Hussein Nili, Xiaolin Xu, Wayne P. Burleson, Omid Kavehei, Marten van Dijk, Damith Chinthana Ranasinghe, Ulrich Rührmair:
Efficient Erasable PUFs from Programmable Logic and Memristors. IACR Cryptol. ePrint Arch. 2018: 358 (2018) - 2017
- [j4]Hao-Ting Shen, Fahim Rahman, Bicky Shakya, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte:
Poly-Si-Based Physical Unclonable Functions. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3207-3217 (2017) - [j3]Fahim Rahman, Bicky Shakya, Xiaolin Xu, Domenic Forte, Mark M. Tehranipoor:
Security Beyond CMOS: Fundamentals, Applications, and Roadmap. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3420-3433 (2017) - [c13]Zimu Guo, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte:
MPA: Model-assisted PCB attestation via board-level RO and temperature compensation. AsianHOST 2017: 25-30 - [c12]Xiaolin Xu, Bicky Shakya, Mark M. Tehranipoor, Domenic Forte:
Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks. CHES 2017: 189-210 - [c11]Zimu Guo, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte:
FFD: A Framework for Fake Flash Detection. DAC 2017: 8:1-8:6 - [c10]Shuo Li, Xiaolin Xu, Wayne P. Burleson:
CCATDC: A Configurable Compact Algorithmic Time-to-Digital Converter. ISVLSI 2017: 501-506 - [c9]Sreeja Chowdhury, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte:
Aging resilient RO PUF with increased reliability in FPGA. ReConFig 2017: 1-7 - [i5]Xiaolin Xu, Bicky Shakya, Mark M. Tehranipoor, Domenic Forte:
Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks. IACR Cryptol. ePrint Arch. 2017: 621 (2017) - 2016
- [c8]Xiaolin Xu, Daniel E. Holcomb:
Reliable PUF design using failure patterns from time-controlled power gating. DFT 2016: 135-140 - [c7]Xiaolin Xu, Daniel E. Holcomb:
A Clockless Sequential PUF with Autonomous Majority Voting. ACM Great Lakes Symposium on VLSI 2016: 27-32 - [c6]Xiaolin Xu, Wayne P. Burleson, Daniel E. Holcomb:
Using Statistical Models to Improve the Reliability of Delay-Based PUFs. ISVLSI 2016: 547-552 - 2015
- [j2]Xiaolin Xu, Amir Rahmati, Daniel E. Holcomb, Kevin Fu, Wayne P. Burleson:
Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6): 903-914 (2015) - [c5]Xiaolin Xu, Ulrich Rührmair, Daniel E. Holcomb, Wayne P. Burleson:
Security Evaluation and Enhancement of Bistable Ring PUFs. RFIDSec 2015: 3-16 - [c4]Ulrich Rührmair, J. L. Martinez-Hurtado, Xiaolin Xu, Christian Kraeh, Christian Hilgers, Dima Kononchuk, Jonathan J. Finley, Wayne P. Burleson:
Virtual Proofs of Reality and their Physical Implementation. IEEE Symposium on Security and Privacy 2015: 70-85 - [i4]Xiaolin Xu, Ulrich Rührmair, Daniel E. Holcomb, Wayne P. Burleson:
Security Evaluation and Enhancement of Bistable Ring PUFs. IACR Cryptol. ePrint Arch. 2015: 443 (2015) - [i3]Chenglu Jin, Xiaolin Xu, Wayne P. Burleson, Ulrich Rührmair, Marten van Dijk:
PLayPUF: Programmable Logically Erasable PUFs for Forward and Backward Secure Key Management. IACR Cryptol. ePrint Arch. 2015: 1052 (2015) - 2014
- [c3]Ulrich Rührmair, Xiaolin Xu, Jan Sölter, Ahmed Mahmoud, Mehrdad Majzoobi, Farinaz Koushanfar, Wayne P. Burleson:
Efficient Power and Timing Side Channels for Physical Unclonable Functions. CHES 2014: 476-492 - [c2]Xiaolin Xu, Wayne P. Burleson:
Hybrid side-channel/machine-learning attacks on PUFs: A new threat? DATE 2014: 1-6 - [c1]Xiaolin Xu, Vikram B. Suresh, Raghavan Kumar, Wayne P. Burleson:
Post-Silicon Validation and Calibration of Hardware Security Primitives. ISVLSI 2014: 29-34 - 2013
- [j1]Ulrich Rührmair, Jan Sölter, Frank Sehnke, Xiaolin Xu, Ahmed Mahmoud, Vera Stoyanova, Gideon Dror, Jürgen Schmidhuber, Wayne P. Burleson, Srinivas Devadas:
PUF Modeling Attacks on Simulated and Silicon Data. IEEE Trans. Inf. Forensics Secur. 8(11): 1876-1891 (2013) - [i2]Ulrich Rührmair, Jan Sölter, Frank Sehnke, Xiaolin Xu, Ahmed Mahmoud, Vera Stoyanova, Gideon Dror, Jürgen Schmidhuber, Wayne P. Burleson, Srinivas Devadas:
PUF Modeling Attacks on Simulated and Silicon Data. IACR Cryptol. ePrint Arch. 2013: 112 (2013) - [i1]Ulrich Rührmair, Xiaolin Xu, Jan Sölter, Ahmed Mahmoud, Farinaz Koushanfar, Wayne P. Burleson:
Power and Timing Side Channels for PUFs and their Efficient Exploitation. IACR Cryptol. ePrint Arch. 2013: 851 (2013)
Coauthor Index
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