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ORCIDMasahiro Goshima
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2020 – today
- 2023
[c26]Yi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya, Masahiro Goshima:
Out-of-Step Pipeline for Gather/Scatter Instructions. DATE 2023: 1-2
2010 – 2019
- 2019
- [c25]Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima:
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. FPT 2019: 63-71 - 2018
- [j12]Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
:
Bank-Aware Instruction Scheduler for a Multibanked Register File. J. Inf. Process. 26: 696-705 (2018) - [c24]Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando:
A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode. ARCS 2018: 211-224 - [c23]Ushio Jimbo, Ryota Shioya, Masahiro Goshima:
Application of Timing Fault Detection to Rocket Core on FPGA. CANDAR Workshops 2018: 178-181 - [c22]Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura:
Isolation-Safe Speculative Access Control for Hardware Transactional Memory. ICECS 2018: 517-520 - [c21]Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura:
An Analysis and a Solution of False Conflicts for Hardware Transactional Memory. ICECS 2018: 529-532 - 2017
- [j11]Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. IEICE Trans. Electron. 100-C(3): 232-244 (2017) - [j10]Ushio Jimbo, Junji Yamada, Ryota Shioya, Masahiro Goshima:
Applying Razor Flip-Flops to SRAM Read Circuits. IEICE Trans. Electron. 100-C(3): 245-258 (2017) - [j9]Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency. IEICE Trans. Inf. Syst. 100-D(4): 822-837 (2017) - [c20]Tomoki Tajimi, Anju Hirota, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura:
Initial study of a phase-aware scheduling for hardware transactional memory. PACRIM 2017: 1-6 - 2016
- [j8]Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando:
FXA: Executing Instructions in Front-End for Energy Efficiency. IEICE Trans. Inf. Syst. 99-D(4): 1092-1107 (2016) - [j7]Minseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai:
An Inductive Method to Select Simulation Points. IEICE Trans. Inf. Syst. 99-D(12): 2891-2900 (2016) - 2015
- [j6]Naruki Kurata, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
Address Order Violation Detection with Parallel Counting Bloom Filters. IEICE Trans. Electron. 98-C(7): 580-593 (2015) - [c19]Minseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai:
An Inductive Method to Select Simulation Points. CANDAR 2015: 392-395 - 2014
- [c18]Koki Murakami, Tsuyoshi Yamada, Rie Shigetomi Yamaguchi, Masahiro Goshima, Shuichi Sakai:
A cloud architecture for protecting guest's information from malicious operators with memory management. CODASPY 2014: 155-158 - [c17]Ryota Shioya, Masahiro Goshima, Hideki Ando:
A Front-End Execution Architecture for High Energy Efficiency. MICRO 2014: 419-431 - 2013
- [j5]Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai:
Register Indirect Jump Target Forwarding. IEICE Trans. Inf. Syst. 96-D(2): 278-288 (2013) - 2011
- [j4]Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai:
Low-Overhead Architecture for Security Tag. IEICE Trans. Inf. Syst. 94-D(1): 69-78 (2011) - 2010
- [c16]Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai:
Register Cache System Not for Latency Reduction Purpose. MICRO 2010: 301-312
2000 – 2009
- 2009
- [c15]Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai:
Low-Overhead Architecture for Security Tag. PRDC 2009: 135-142 - [c14]Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
String-Wise Information Flow Tracking against Script Injection Attacks. PRDC 2009: 169-176 - 2008
- [j3]Shuichi Sakai, Masahiro Goshima, Hidetsugu Irie:
Ultra Dependable Processor. IEICE Trans. Electron. 91-C(9): 1386-1393 (2008) - [c13]Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita:
Low-Complexity Bypass Network Using Small RAM. CDES 2008: 153-159 - 2007
- [j2]Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai:
Preventing timing errors on register writes: mechanisms of detections and recoveries. SIGARCH Comput. Archit. News 35(5): 25-31 (2007) - [c12]Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai:
Utilization of SECDED for soft error and variation-induced defect tolerance in caches. DATE 2007: 1134-1139 - 2006
- [c11]Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai:
SEVA: A Soft-Error- and Variation-Aware Cache Architecture. PRDC 2006: 47-54 - [c10]Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai:
Base Address Recognition with Data Flow Tracking for Injection Attack Detection. PRDC 2006: 165-172 - 2005
- [c9]Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai:
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. ICCD 2005: 342-350 - 2004
- [c8]Motohiro Takayama, Yuki Shinomoto, Masahiro Goshima, Shin-ichiro Mori, Yasuhiko Nakashima, Shinji Tomita:
Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing. PDPTA 2004: 373-382 - 2001
- [c7]Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori:
A high-speed dynamic instruction scheduling scheme for superscalar processors. MICRO 2001: 225-236
1990 – 1999
- 1999
- [j1]Atsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita:
A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR. Int. J. Parallel Program. 27(2): 97-109 (1999) - 1998
- [c6]Shin-ya Goto, Atsushi Kubota, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita:
Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPAR. IEEE PACT 1998: 426-433 - 1997
- [c5]Kazuhiko Ohno, Masahiko Ikawa, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita:
Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis. ASIAN 1997: 268-282 - [c4]Kazuhiko Ohno, Masahiko Ikawa, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita, Masahiro Goshima:
Improvement of message communication in concurrent logic language. PASCO 1997: 156-164 - [c3]Atsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita:
A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR. ISHPC 1997: 195-204 - 1995
- [c2]Shin-ichiro Mori, Masahiro Goshima, Hiroshi Nakashima, Shinji Tomita:
A proposal of self-cleanup cache. PACT 1995: 298-301 - 1993
- [c1]Shin-ichiro Mori, Hideki Saito, Masahiro Goshima, Mamoru Yanagihara, Takashi Tanaka, David Fraser, Kazuki Joe, Hiroyuki Nitta, Shinji Tomita:
A distributed shared memory multiprocessor ASURA: memory and cache architecture. SC 1993: 740-749
Coauthor Index
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