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ORCIDTom Eeckelaert
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2020 – today
- 2024
[c10]Dirk Pfaff, Muhammad Nummer, Noman Hai, Peter Xia, Kai Ge Yang
, Mohammad-Mahdi Mohsenpour, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson Dick, Alif Zaman, Haitao Mei, Shahab Moazzeni, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Brishty, Ifrah Jaffri:
7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS. ISSCC 2024: 128-130
2000 – 2009
- 2007
- [c9]Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen:
An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection. DATE 2007: 81-86 - [c8]Georges G. E. Gielen, Tom Eeckelaert, Ewout Martens, Trent McConaghy:
Automated synthesis of complex analog circuits. ECCTD 2007: 20-23 - [i1]Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen:
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming. CoRR abs/0710.4630 (2007) - 2006
- [c7]Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen:
Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard. DAC 2006: 25-30 - [c6]Raf Schoofs, Tom Eeckelaert, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen:
A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology. ICECS 2006: 950-953 - 2005
- [c5]Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert:
Performance space modeling for hierarchical synthesis of analog integrated circuits. DAC 2005: 881-886 - [c4]Tom Eeckelaert, Trent McConaghy, Georges G. E. Gielen:
Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces. DATE 2005: 1070-1075 - [c3]Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen:
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming. DATE 2005: 1082-1087 - [c2]Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen:
CAFFEINE: template-free symbolic model generation of analog circuits via canonical form functions and genetic programming. ESSCIRC 2005: 243-246 - 2003
- [c1]Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Generalized Posynomial Performance Modeling. DATE 2003: 10250-10255
Coauthor Index
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