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2020 – today
- 2023
[c30]Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio
, Valentin Puente:
Performance Characterization of Popular DNN Models on Out-of-Order CPUs. PACT 2023: 199-210- 2022
- [c29]Alvaro Saiz, Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente:
Top-Down Performance Profiling on NVIDIA's GPUs. IPDPS 2022: 179-189 - 2021
- [j18]Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente:
Fast, Accurate Processor Evaluation Through Heterogeneous, Sample-Based Benchmarking. IEEE Trans. Parallel Distributed Syst. 32(12): 2983-2995 (2021) - 2020
- [j17]Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio:
Rainbow: A composable coherence protocol for multi-chip servers. Concurr. Comput. Pract. Exp. 32(24) (2020) - [c28]Pablo Prieto, Pablo Abad Fidalgo, Jose Angel Herrero, José-Ángel Gregorio, Valentin Puente:
SPECcast: A Methodology for Fast Performance Evaluation with SPEC CPU 2017 Multiprogrammed Workloads. ICPP 2020: 54:1-54:11 - [i5]Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio:
Rainbow: A Composable Coherence Protocol for Multi-Chip Servers. CoRR abs/2002.03944 (2020)
2010 – 2019
- 2019
- [j16]Valentin Puente, José-Ángel Gregorio:
CLASSIC: A cortex-inspired hardware accelerator. J. Parallel Distributed Comput. 134: 140-152 (2019) - [c27]Adrian Colaso, Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente:
Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms. IPDPS 2019: 273-282 - [i4]Adrian Colaso, Pablo Prieto, Jose Angel Herrero, Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio:
Accuracy vs. Computational Cost Tradeoff in Distributed Computer System Simulation. CoRR abs/1902.02837 (2019) - 2018
- [j15]Lucia G. Menezo, Valentin Puente, Pablo Abad Fidalgo, José-Ángel Gregorio:
Mosaic: A Scalable Coherence Protocol. Int. J. Parallel Program. 46(6): 1110-1138 (2018) - [j14]Adrian Colaso, Pablo Prieto, Jose Angel Herrero, Pablo Abad Fidalgo, Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio:
Memory Hierarchy Characterization of NoSQL Applications through Full-System Simulation. IEEE Trans. Parallel Distributed Syst. 29(5): 1161-1173 (2018) - 2017
- [j13]Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio:
An adaptive cache coherence protocol: Trading storage for traffic. J. Parallel Distributed Comput. 102: 163-174 (2017) - 2016
- [j12]Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio:
AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory. IEEE Trans. Parallel Distributed Syst. 27(1): 66-77 (2016) - [i3]Valentin Puente, José-Ángel Gregorio:
CLAASIC: a Cortex-Inspired Hardware Accelerator. CoRR abs/1604.05897 (2016) - 2015
- [j11]Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio:
Improving last level shared cache performance through mobile insertion policies (MIP). Parallel Comput. 49: 13-27 (2015) - [c26]Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio:
Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalability. HPCA 2015: 198-209 - 2014
- [c25]Philip G. Emma, Alper Buyuktosunoglu, Michael B. Healy, Krishnan Kailas, Valentin Puente, Roy Yu, Allan Hartstein, Pradip Bose, Jaime H. Moreno, Eren Kursun:
3D stacking of high-performance processors. HPCA 2014: 500-511 - 2013
- [j10]Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio:
LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors. ACM Trans. Archit. Code Optim. 9(4): 37:1-37:21 (2013) - [c24]Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio:
The case for a scalable coherence protocol for complex on-chip cache hierarchies in many-core systems. PACT 2013: 279-288 - [c23]Pablo Abad Fidalgo, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio:
Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs. DSD 2013: 48-55 - [c22]Pablo Prieto, Valentin Puente, José-Ángel Gregorio:
CMP off-chip bandwidth scheduling guided by instruction criticality. ICS 2013: 379-388 - 2012
- [j9]Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio:
Balancing Performance and Cost in CMP Interconnection Networks. IEEE Trans. Parallel Distributed Syst. 23(3): 452-459 (2012) - [j8]Pablo Abad Fidalgo, Valentin Puente, Lucia G. Menezo, José-Ángel Gregorio:
Adaptive-Tree Multicast: Efficient Multidestination Support for CMP Communication Substrate. IEEE Trans. Parallel Distributed Syst. 23(11): 2010-2023 (2012) - [c21]Lucia G. Menezo, Valentin Puente, Pablo Abad Fidalgo, José-Ángel Gregorio:
Improving coherence protocol reactiveness by trading bandwidth for latency. Conf. Computing Frontiers 2012: 143-152 - [c20]Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio:
BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip. ICCD 2012: 55-60 - [c19]Pablo Abad Fidalgo, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio:
TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers. NOCS 2012: 99-106 - [i2]Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio:
LOCKE Detailed Specification Tables. CoRR abs/1203.5349 (2012) - [i1]Javier Merino, Valentin Puente, José-Ángel Gregorio:
The Necessity for Hardware QoS Support for Server Consolidation and Cloud Computing. CoRR abs/1206.6213 (2012) - 2011
- [j7]Pablo Prieto, Valentin Puente, José-Ángel Gregorio:
Multilevel Cache Modeling for Chip-Multiprocessor Systems. IEEE Comput. Archit. Lett. 10(2): 49-52 (2011) - 2010
- [c18]Javier Merino, Valentin Puente, José-Ángel Gregorio:
ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture. HPCA 2010: 1-10
2000 – 2009
- 2009
- [c17]Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio:
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks. HPCA 2009: 355-366 - 2008
- [j6]Javier Merino, Valentin Puente, Pablo Prieto, José-Ángel Gregorio:
SP-NUCA: a cost effective dynamic non-uniform cache architecture. SIGARCH Comput. Archit. News 36(2): 64-71 (2008) - [j5]Valentin Puente, José-Ángel Gregorio, Fernando Vallejo, Ramón Beivide:
Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology. IEEE Trans. Computers 57(12): 1676-1689 (2008) - [c16]Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio:
Reducing the Interconnection Network Cost of Chip Multiprocessors. NOCS 2008: 183-192 - 2007
- [j4]Valentin Puente, José-Ángel Gregorio:
Immucube: Scalable Fault-Tolerant Routing for k-ary n-cube Networks. IEEE Trans. Parallel Distributed Syst. 18(6): 776-788 (2007) - [c15]Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio, Pablo Prieto:
Rotary router: an efficient architecture for CMP interconnection networks. ISCA 2007: 116-125 - 2006
- [j3]Valentin Puente, José A. Gregorio, Fernando Vallejo, Ramón Beivide, Cruz Izu:
High-performance adaptive routing for networks with arbitrary topology. J. Syst. Archit. 52(6): 345-358 (2006) - 2004
- [c14]Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero:
A first glance at Kilo-instruction based multiprocessors. Conf. Computing Frontiers 2004: 212-221 - [c13]José Miguel-Alonso, José A. Gregorio, Valentin Puente, Fernando Vallejo, Ramón Beivide:
Load Unbalance in k-ary n-Cube Networks. Euro-Par 2004: 900-907 - [c12]Valentin Puente, José A. Gregorio, Fernando Vallejo, Ramón Beivide:
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism. ISCA 2004: 198-211 - [c11]Luis A. Amigo, Valentin Puente, José-Ángel Gregorio:
Simulation Methodology for Decision Support Workloads. PDP 2004: 120-125 - [c10]Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero:
Evaluating kilo-instruction multiprocessors. WMPI 2004: 72-79 - 2003
- [j2]Valentin Puente, José A. Gregorio, Ramón Beivide, Cruz Izu:
On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors. IEEE Trans. Parallel Distributed Syst. 14(5): 487-501 (2003) - [c9]Valentin Puente, José A. Gregorio, Ramón Beivide, Fernando Vallejo:
A Low Cost Fault Tolerant Packet Routing for Parallel Computers. IPDPS 2003: 45 - 2002
- [c8]Valentin Puente, José A. Gregorio, Ramón Beivide:
SICOSYS: An Integrated Framework for studying Interconnection Network Performance in Multiprocessor Systems. PDP 2002: 15-22 - 2001
- [j1]Valentin Puente, Cruz Izu, Ramón Beivide, José A. Gregorio, Fernando Vallejo, J. M. Prellezo:
The Adaptive Bubble Router. J. Parallel Distributed Comput. 61(9): 1180-1208 (2001) - [c7]Andres Ibañez, Valentin Puente, José A. Gregorio, Ramón Beivide:
A New Communication Mechanism for Cluster Computing. Euro-Par 2001: 793-800 - [c6]Valentin Puente, José A. Gregorio, Ramón Beivide, Fernando Vallejo, Andres Ibañez:
A new routing mechanism for networks with irregular topology. SC 2001: 31 - 2000
- [c5]Valentin Puente, Cruz Izu, José A. Gregorio, Ramón Beivide, J. M. Prellezo, Fernando Vallejo:
Improving parallel system performance by changing the arrangement of the network links. ICS 2000: 44-53 - [c4]Valentin Puente, J. M. Prellezo, Cruz Izu, José-Ángel Gregorio, Ramón Beivide:
A case study of trace-driven simulation for analyzing interconnection networks: cc-NUMAs with ILP processors. PDP 2000: 174-180
1990 – 1999
- 1999
- [c3]Valentin Puente, José A. Gregorio, Cruz Izu, Ramón Beivide:
Impact of the Head-of-Line Blocking on Parallel Computer Networks: Hardware to Applications. Euro-Par 1999: 1222-1230 - [c2]Valentin Puente, Ramón Beivide, José A. Gregorio, J. M. Prellezo, José Duato, Cruz Izu:
Adaptive Bubble Router: A Design to Improve Performance in Torus Networks. ICPP 1999: 58-67 - [c1]Valentin Puente, José A. Gregorio, Cruz Izu, Ramón Beivide, Fernando Vallejo:
Low-level router design and its impact on supercomputer system performance. International Conference on Supercomputing 1999: 193-201
Coauthor Index
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