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ORCIDYukio Miyasaka
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2020 – today
- 2024
[c10]Yukio Miyasaka:
Transduction Method for AIG Minimization. ASPDAC 2024: 398-403- [c9]Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Nicholas J. Fraser:
Synthesis of LUT Networks for Random-Looking Dense Functions with Don't Cares - Towards Efficient FPGA Implementation of DNN. FCCM 2024: 126-132 - 2023
- [j3]Jitendra Kumar
, Yukio Miyasaka, Asutosh Srivastava, Masahiro Fujita:
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1365-1378 (2023) - 2022
- [j2]Mingfei Yu, Yukio Miyasaka, Masahiro Fujita:
Parallel Scheduling Attention Mechanism: Generalization and Optimization. IPSJ Trans. Syst. LSI Des. Methodol. 15: 2-15 (2022) - 2021
- [c8]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - [c7]Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita:
Logic Synthesis for Generalization and Learning Addition. DATE 2021: 1032-1037 - 2020
- [j1]Yukio Miyasaka, Akihiro Goda, Ashish Mittal, Masahiro Fujita:
Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication. IPSJ Trans. Syst. LSI Des. Methodol. 13: 31-34 (2020) - [c6]Masahiro Fujita, Yusuke Kimura, Xingming Le, Yukio Miyasaka, Amir Masoud Gharehbaghi:
Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations. DATE 2020: 744-749 - [c5]Akihiro Goda, Yukio Miyasaka, Amir Masoud Gharehbaghi, Masahiro Fujita:
Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints. ISQED 2020: 123-128 - [c4]Yukio Miyasaka, Masahiro Fujita:
SAT-Based Data-Flow Mapping Onto Array Processor. VLSI-SOC 2020: 22-27 - [c3]Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek:
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. VLSI-SoC (Selected Papers) 2020: 113-131 - [i1]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)
2010 – 2019
- 2019
- [c2]Tomohiro Maruoka, Yukio Miyasaka, Akihiro Goda, Amir Masoud Gharehbaghi, Masahiro Fujita:
Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints. ISCAS 2019: 1 - [c1]Yukio Miyasaka, Ashish Mittal, Masahiro Fujita:
Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing. ISQED 2019: 45-51
Coauthor Index
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