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ORCIDS. Gurunarayanan 0001
Person information
- affiliation: Birla Institute of Technology and Science Pilani, Rajasthan, India
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2020 – today
- 2024
[j10]Aalelai Vendhan
, Syed Ershad Ahmed, S. Gurunarayanan:
Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders. Circuits Syst. Signal Process. 43(7): 4050-4072 (2024)- 2022
- [c13]Kanika Monga, Eesha Karnawat, Nitin Chaturvedi, S. Gurunarayanan:
Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations. VDAT 2022: 408-419 - 2021
- [j9]Kanika Monga, Kunal Harbhajanka, Arush Srivastava, Nitin Chaturvedi, S. Gurunarayanan:
Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications. J. Circuits Syst. Comput. 30(4): 2150058:1-2150058:14 (2021) - 2020
- [j8]G. Sai Sesha Chalapathi, Vinay Chamola, Chen-Khong Tham, S. Gurunarayanan, Nirwan Ansari:
An optimal delay aware task assignment scheme for wireless SDN networked edge cloudlets. Future Gener. Comput. Syst. 102: 862-875 (2020) - [c12]Kanika Monga, Lakshaya Maheshwari, Nitin Chaturvedi, S. Gurunarayanan:
Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array. VDAT 2020: 1-4
2010 – 2019
- 2019
- [j7]Kanika, R. Sankara Prasad, Nitin Chaturvedi, S. Gurunarayanan:
A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications. Integr. 65: 43-50 (2019) - [j6]G. Sai Sesha Chalapathi, Vinay Chamola, S. Gurunarayanan:
A testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT. J. Intell. Fuzzy Syst. 36(5): 4531-4543 (2019) - [j5]G. Sai Sesha Chalapathi, Bernhard Etzlinger, S. Gurunarayanan, Andreas Springer:
Integrated Cooperative Synchronization for Wireless Sensor Networks. IEEE Wirel. Commun. Lett. 8(3): 701-704 (2019) - 2017
- [j4]D. C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, Munish Bhatia:
Register allocation for fine grain threads on multicore processor. J. King Saud Univ. Comput. Inf. Sci. 29(1): 85-92 (2017) - 2015
- [j3]Nitin Chaturvedi, S. Gurunarayanan:
An efficient adaptive block pinning for multicore architectures. Microprocess. Microsystems 39(3): 181-188 (2015) - [j2]D. C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, Abhijeet Nawal:
Global Scheduling Heuristics for Multicore Architecture. Sci. Program. 2015: 860891:1-860891:12 (2015) - [j1]Nitin Chaturvedi, Arun Subramaniyan, S. Gurunarayanan:
An adaptive migration-replication scheme (AMR) for shared cache in chip multiprocessors. J. Supercomput. 71(10): 3904-3933 (2015) - [c11]Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
An embedded framework for accurate object localization using center of gravity measure with mean shift procedure. VDAT 2015: 1-6 - [c10]Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications. VLSID 2015: 339-344 - 2014
- [c9]Jai Gopal Pandey, Arindam Karmakar, S. Gurunarayanan:
Architectures and algorithms for image and video processing using FPGA-based platform. VDAT 2014: 1 - [c8]Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm. VLSID 2014: 300-305 - 2013
- [c7]Munish Bhatia, D. C. Kiran, Janardan Prasad Misra, S. Gurunarayanan:
Fine grain thread scheduling on multicore processors: cores with multiple functional units. COMPUTE 2013: 20:1-20:6 - 2012
- [c6]D. C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, Faizan Khaliq:
An efficient method to compute static single assignment form for multicore architecture. RAIT 2012: 776-781
2000 – 2009
- 2008
- [c5]Biju K. Raveendran, Sundar Balasubramaniam, S. Gurunarayanan:
Evaluation of priority based real time scheduling algorithms: choices and tradeoffs. SAC 2008: 302-307 - 2007
- [c4]Biju K. Raveendran, Janardan Prasad Misra, Karan Bhatnagar, S. Gurunarayanan:
EFFS: Efficient Flash File System for Wireless Sensor Nodes. ESA 2007: 159-168 - [c3]Biju K. Raveendran, T. S. B. Sudarshan, Avinash Patil, Komal B. Randive, S. Gurunarayanan:
An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System. ESA 2007: 188-196 - 2006
- [c2]Biju K. Raveendran, Sundar Balasubramaniam, K. Durga Prasad, S. Gurunarayanan:
A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling. Asia-Pacific Computer Systems Architecture Conference 2006: 437-444 - [c1]Biju K. Raveendran, K. Durga Prasad, Sundar Balasubramaniam, S. Gurunarayanan:
Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems. ICDCN 2006: 466-478
Coauthor Index
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