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ORCIDChunduri Rama Mohan
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2020 – today
- 2020
[j3]Sudipa Mandal
, Pallab Dasgupta, Aritra Hazra, Chunduri Rama Mohan:
Assertions for Protecting Mixed-Signal Latency Contracts in Power Management. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1745-1756 (2020)
2010 – 2019
- 2018
- [c14]Sudipa Mandal, Aritra Hazra, Pallab Dasgupta, Chunduri Rama Mohan:
Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components. VLSID 2018: 37-42 - 2017
- [c13]Sudipa Mandal, Antonio Anastasio Bruto da Costa, Aritra Hazra, Pallab Dasgupta, Bhushan Naware, Chunduri Rama Mohan, Sanjib Basu:
Formal Verification of Power Management Logic with Mixed-Signal Domains. VLSID 2017: 239-244
2000 – 2009
- 2008
- [c12]Aritra Hazra, Ansuman Banerjee, Srobona Mitra, Pallab Dasgupta, Partha Pratim Chakrabarti, Chunduri Rama Mohan:
Cohesive Coverage Management for Simulation and Formal Property Verification. ISVLSI 2008: 251-256 - 2007
- [c11]Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama Mohan:
An ECO Technique for Removing Crosstalk Violations in Clock Networks. VLSI Design 2007: 283-288 - 2006
- [j2]Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni:
Design-Intent Coverage - A New Paradigm for Formal Property Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 1922-1934 (2006) - 2005
- [c10]Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix:
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model. VLSI Design 2005: 201-206 - 2004
- [c9]Prasenjit Basu, Sayantan Das, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix:
Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? DATE 2004: 668-669 - [c8]Sayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni:
Formal verification coverage: computing the coverage gap between temporal specifications. ICCAD 2004: 198-203 - [c7]Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan:
Property Refinement Techniques for Enhancing Coverage of Formal Property Verification. VLSI Design 2004: 109-114
1990 – 1999
- 1997
- [c6]Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri:
On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. VLSI Design 1997: 547-563 - 1996
- [j1]Chunduri Rama Mohan, Partha Pratim Chakrabarti:
EARTH: combined state assignment of PLA-based FSM's targeting area and testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7): 727-731 (1996) - 1995
- [c5]Chunduri Rama Mohan, Partha Pratim Chakrabarti:
Combined optimization of area and testability during state assignment of PLA-based FSM's. VLSI Design 1995: 408-413 - 1994
- [c4]Chunduri Rama Mohan, Partha Pratim Chakrabarti:
A new approach for factorizing FSM's. ICCAD 1994: 698-701 - [c3]Chunduri Rama Mohan, Partha Pratim Chakrabarti:
A New Approach to Synthesis of PLA-Based FSM's. VLSI Design 1994: 373-378 - 1993
- [c2]Chunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose:
Combining State Assignment with PLA Folding. VLSI Design 1993: 9-14 - 1992
- [c1]Chunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose:
A New algorithm for combined PLA folding. VLSI Design 1992: 368-369
Coauthor Index
aka: Partha Pratim Chakrabarti
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