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2020 – today
- 2024
[c13]Yufeng Xie, Yinan Wang, Han Wang, Qingshan Li:
Self-Supervised Reinforcement Learning for Out-of-Distribution Recovery via Auxiliary Reward. ICASSP 2024: 7725-7729- 2023
- [j11]Sikang Chen, Jian Gao, Jiexuan Chen, Yufeng Xie, Zheyuan Shen, Lei Xu, Jinxin Che, Jian Wu, Xiaowu Dong:
ClusterX: a novel representation learning-based deep clustering framework for accurate visual inspection in virtual screening. Briefings Bioinform. 24(3) (2023) - [j10]Jian Gao, Zheyuan Shen, Yufeng Xie, Jialiang Lu, Yang Lu
, Sikang Chen, Qingyu Bian, Yue Guo, Liteng Shen, Jian Wu, Binbin Zhou, Tingjun Hou, Qiaojun He, Jinxin Che, Xiaowu Dong:
TransFoxMol: predicting molecular property with focused attention. Briefings Bioinform. 24(5) (2023) - [j9]Xianwu Hu, Yu Wang, Zizhao Ma, Gan Wen, Zeming Wang, Zhichao Lu, Yunlong Liu, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie:
An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4216-4220 (2023) - [c12]Zizhao Ma, Xianwu Hu, Gan Wen, Yihao Wang, Zeming Wang, Yukai Lin, Yu Wang, Yuhao Guo, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie:
GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications. A-SSCC 2023: 1-3 - [c11]Zizhao Ma, Xianwu Hu, Yihao Wang, Gan Wen, Xiaoyang Zeng, Yufeng Xie:
A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation. ISCAS 2023: 1-5 - 2022
- [c10]Yufeng Xie, Mingchu Li, Kun Lu, Syed Bilal Hussain Shah, Xiao Zheng:
Multi-task Learning Model based on Multiple Characteristics and Multiple Interests for CTR prediction. DSC 2022: 1-7 - [c9]Xianwu Hu, Yu Wang, Jiayun Feng, Zizhao Ma, Xiaoyang Zeng, Yufeng Xie:
A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process. ISCAS 2022: 2438-2442 - 2021
- [c8]Xianwu Hu, Dongyang Li, Yu Wang, Jiayun Feng, Zizhao Ma, Shaohao Wang, Tai Min, Xiaoyang Zeng, Yufeng Xie:
An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process. ASICON 2021: 1-4 - [c7]Yukai Lin, Yu Wang, Xianwu Hu, Jiayun Feng, Gan Wen, Xiankui Xiong, Haidong Tian, Yufeng Xie:
A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight. ASICON 2021: 1-4 - [c6]Ruiwei Feng, Yufeng Xie, Minshan Lai, Danny Z. Chen, Ji Cao, Jian Wu:
AGMI: Attention-Guided Multi-omics Integration for Drug Response Prediction with Graph Neural Networks. BIBM 2021: 1295-1298 - [i1]Ruiwei Feng, Yufeng Xie, Minshan Lai, Danny Z. Chen, Ji Cao, Jian Wu:
AGMI: Attention-Guided Multi-omics Integration for Drug Response Prediction with Graph Neural Networks. CoRR abs/2112.08366 (2021) - 2020
- [c5]Zhiwei Zhang, Hui Hou, Min Li, Yufeng Xie, Ling Zhu, Yong Huang:
Weighted Failure Probability Calculation of Overhead Distribution Line in Random Wind Field. SSCI 2020: 968-975
2010 – 2019
- 2019
- [j8]Yufeng Xie, Zhi Liu, Xiaofei Zhou, Wei Liu, Xuemei Zou:
Video co-segmentation based on directed graph. Multim. Tools Appl. 78(8): 10353-10372 (2019) - [c4]Danqing Wu, Shilin Yan, Haodi Tang, Yu Wang, Jiayun Feng, Xianwu Hu, Jiaxin Cao, Yufeng Xie:
A digitalized RRAM-based Spiking Neuron Network system with 3-bit weight and unsupervised online learning scheme. ASICON 2019: 1-4 - 2017
- [j7]Xiaoyong Xue, Yarong Fu, Yanqing Zhao, Juan Xu, Jianguo Yang, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 186-190 (2017) - 2016
- [j6]Hangke Song, Zhi Liu, Yufeng Xie, Lishan Wu, Mengke Huang:
RGBD Co-saliency Detection via Bagging-Based Clustering. IEEE Signal Process. Lett. 23(12): 1722-1726 (2016) - [j5]Yufeng Xie, Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Qingtian Zou, Ryan Huang, Jingang Wu:
A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 336-340 (2016) - 2013
- [j4]Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, Fanjie Xiao, Gang Chen, Shuliu Xu, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
A 0.13 µm 8 Mb Logic-Based Cux Siy O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction. IEEE J. Solid State Circuits 48(5): 1315-1322 (2013) - 2012
- [j3]Yufeng Xie, Wenxiang Jian, Xiaoyong Xue, Gang Jin, Yinyin Lin:
64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage. IEICE Electron. Express 9(12): 1051-1056 (2012) - 2011
- [j2]Xiaoyong Xue, Yufeng Xie, Yinyin Lin:
Novel 2T programmable element to improve density and performance of FPGA. IEICE Electron. Express 8(7): 454-459 (2011) - [c3]Bing Yan, Yufeng Xie, Rui Yuan, Yinyin Lin:
A BIST scheme for high-speed Gain Cell eDRAM. ASICON 2011: 244-247 - [c2]Xiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin:
Novel RRAM programming technology for instant-on and high-security FPGAs. ASICON 2011: 291-294 - 2010
- [j1]Ji Zhang, Yiqing Ding, Xiaoyong Xue, Gang Jin, Yuxin Wu, Yufeng Xie, Yinyin Lin:
A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell. IEICE Trans. Electron. 93-C(12): 1692-1699 (2010)
2000 – 2009
- 2007
- [c1]Yufeng Xie, Leibo Liu, Rui Dai, Shaojun Wei:
Battery-Aware Variable Voltage Scheduling on Real-Time Multiprocessor Platforms. ISCAS 2007: 1883-1886
Coauthor Index
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last updated on 2024-10-07 21:22 CEST by the dblp team
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