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ORCIDShigeru Oyanagi
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2010 – 2019
- 2018
[j8]Lin Meng
, Takuma Hirayama, Shigeru Oyanagi:
Underwater-Drone With Panoramic Camera for Automatic Fish Recognition Based on Deep Learning. IEEE Access 6: 17880-17886 (2018)- 2017
- [c16]Lin Meng, Takuma Hirayama, Shigeru Oyanagi:
The Development of Underwater-Drone equipped with 360-degree Panorama Camera in Opensource Hardware. IIKI 2017: 438-442 - 2013
- [j7]Ryohei Ebina, Kenji Nakamura, Shigeru Oyanagi:
A Real-Time Burst Analysis Method. Int. J. Artif. Intell. Tools 22(5) (2013) - 2012
- [i2]Truong Vinh Truong Duy, Katsuhiro Yamazaki, Kosai Ikegami, Shigeru Oyanagi:
Hybrid MPI-OpenMP Paradigm on SMP Clusters: MPEG-2 Encoder and N-Body Simulation. CoRR abs/1211.2292 (2012) - [i1]Truong Vinh Truong Duy, Katsuhiro Yamazaki, Shigeru Oyanagi:
Performance Evaluation of Treecode Algorithm for N-Body Simulation Using GridRPC System. CoRR abs/1211.2293 (2012) - 2011
- [c15]Son Truong Nguyen, Shigeru Oyanagi:
An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation. ARCS 2011: 219-230 - [c14]Chu Van Thiem, Shigeru Oyanagi:
An Input Buffer Architecture for On-chip Routers. ICNC 2011: 280-283 - [c13]Ryohei Ebina, Kenji Nakamura, Shigeru Oyanagi:
A Real-Time Burst Detection Method. ICTAI 2011: 1040-1046 - 2010
- [c12]Son Truong Nguyen, Shigeru Oyanagi:
A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks. DSD 2010: 60-67 - [c11]Son Truong Nguyen, Shigeru Oyanagi:
The Design of On-the-Fly Virtual Channel Allocation for Low Cost High Performance On-Chip Routers. ICNC 2010: 88-94 - [c10]Lin Meng, Shigeru Oyanagi:
Control Independence Using Dual Renaming. ICNC 2010: 264-267
2000 – 2009
- 2009
- [j6]Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi:
Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate. IEICE Trans. Inf. Syst. 92-D(10): 2034-2042 (2009) - 2008
- [c9]Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi:
Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding. FCCM 2008: 271-272 - [c8]Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi:
Three-stage pipeline implementation for SHA2 using data forwarding. FPL 2008: 29-34 - 2006
- [c7]Quang Tran Minh, Shigeru Oyanagi, Katsuhiro Yamazaki:
ExMiner: An Efficient Algorithm for Mining Top-K Frequent Patterns. ADMA 2006: 436-447 - [c6]Quang Tran Minh, Shigeru Oyanagi, Katsuhiro Yamazaki:
Mining the K-Most Interesting Frequent Patterns Sequentially. IDEAL 2006: 620-628 - 2004
- [j5]Tran Cong So, Shigeru Oyanagi, Katsuhiro Yamazaki:
Speculative Selection Routing in 2D Torus Network. IEICE Trans. Inf. Syst. 87-D(7): 1666-1673 (2004) - 2002
- [c5]Shigeru Oyanagi, Kazuto Kubota, Akihiko Nakase:
Mining WWW Access Sequence by Matrix Clustering. WEBKDD 2002: 119-136 - 2001
- [c4]Kazuto Kubota, Akihiko Nakase, Shigeru Oyanagi:
Implementation and performance evaluation of dynamic scheduling for parallel decision tree generation. IPDPS 2001: 157
1990 – 1999
- 1996
- [j4]Yasushi Kawakura, Noboru Tanabe, Shigeru Oyanagi:
Improving the performance of global communication on a three-dimensional torus network. Syst. Comput. Jpn. 27(6): 24-32 (1996) - 1994
- [c3]Yasushi Kawakura, Shigeru Oyanagi:
Improving the Performance of Global Communication on a 3D torus network. ICPP (3) 1994: 193-196 - 1992
- [j3]Noboru Tanabe, Sadao Nakamura, Takashi Suzuoka, Shigeru Oyanagi:
Implementation of the prodigy parallel AI machine and performance evaluation of communication. Syst. Comput. Jpn. 23(8): 1-12 (1992) - 1991
- [c2]Noboru Tanabe, Takashi Suzuoka, Sadao Nakamura, Yasushi Kawakura, Shigeru Oyanagi:
Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY. ICPP (1) 1991: 509-516
1980 – 1989
- 1989
- [j2]Takashi Suzuoka, Noboru Tanabe, Sadao Nakamura, Sumikazu Fujita, Shigeru Oyanagi:
Network Performance of the Prodigy Parallel AI Machine. Syst. Comput. Jpn. 20(9): 44-51 (1989) - 1980
- [j1]Hiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama:
A Dynamically Microprogammable Computer with Low-Level Parallelism. IEEE Trans. Computers 29(7): 577-595 (1980)
1970 – 1979
- 1977
- [c1]Shinji Tomita, Kiyoshi Shibayama, Shigeru Oyanagi, Hiroshi Hagiwara:
Hardware Organization of a Low Level Parallel Processor. IFIP Congress 1977: 855-860
Coauthor Index
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