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ORCIDShiann-Rong Kuang
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2020 – today
- 2022
[c9]Xiang-Yu Chen, Yu-Hsiang Wang, Yao-Song Zhang, Yen-Jui Chen, Shiann-Rong Kuang:
Hardware Implementation of an Automatic Color Equalization Algorithm for Real-time Image Enhancement. MCSoC 2022: 174-179
2010 – 2019
- 2017
- [c8]Cheng-Hao Chang, I-Chang Huang, Mu-Fan Lin, Shiann-Rong Kuang:
Design and implementation of a low-cost guided image filter for underwater image enhancement. DSC 2017: 296-299 - 2016
- [j12]Shiann-Rong Kuang, Chih-Yuan Liang, Chun-Chi Chen:
An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication. IEEE Trans. Circuits Syst. II Express Briefs 63-II(6): 568-572 (2016) - [j11]Shiann-Rong Kuang, Kun-Yi Wu, Ren-Yao Lu:
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 434-443 (2016) - 2015
- [c7]Hsu-Kang Dow
, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee:
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. VLSI-DAT 2015: 1-4 - 2014
- [j10]Shiann-Rong Kuang, Kun-Yi Wu, Bao-Chen Ke, Jia-Huei Yeh, Hao-Yi Jheng:
Efficient architecture and hardware implementation of hybrid fuzzy-Kalman filter for workload prediction. Integr. 47(4): 408-416 (2014) - 2013
- [j9]Kun-Yi Wu, Shiann-Rong Kuang, Kee-Khuan Yu:
An exact method for estimating maximum errors of multi-mode floating-point iterative booth multiplier. Int. J. Comput. Sci. Eng. 8(4): 306-315 (2013) - [j8]Shiann-Rong Kuang, Jiun-Ping Wang, Kai-Cheng Chang, Huan-Wei Hsu:
Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 1999-2009 (2013) - [j7]Shiann-Rong Kuang, Kun-Yi Wu, Kee-Khuan Yu:
Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications. J. Signal Process. Syst. 72(1): 43-55 (2013) - [c6]Kun-Yi Wu, Chih-Yuan Liang, Kee-Khuan Yu, Shiann-Rong Kuang:
Multiple-mode floating-point multiply-add fused unit for trading accuracy with power consumption. ICIS 2013: 429-435 - 2011
- [j6]Jiun-Ping Wang, Shiann-Rong Kuang, Shish-Chang Liang:
High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 52-60 (2011) - 2010
- [j5]Shiann-Rong Kuang, Jiun-Ping Wang:
Design of Power-Efficient Configurable Booth Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 568-580 (2010) - [j4]Shiann-Rong Kuang, Jiun-Ping Wang, Hong-Yi Huang:
Variable-Latency Floating-Point Multipliers for Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 18(10): 1493-1497 (2010)
2000 – 2009
- 2009
- [j3]Shiann-Rong Kuang, Jiun-Ping Wang, Cang-Yuan Guo:
Modified Booth Multipliers With a Regular Partial Product Array. IEEE Trans. Circuits Syst. II Express Briefs 56-II(5): 404-408 (2009) - 2007
- [j2]Shiann-Rong Kuang, Jiun-Ping Wang:
Design of power-efficient pipelined truncated multipliers with various output precision. IET Comput. Digit. Tech. 1(2): 129-136 (2007) - [c5]Jiun-Ping Wang, Shiann-Rong Kuang:
Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit. SiPS 2007: 157-162 - 2005
- [c4]Shiann-Rong Kuang, Chin-Yang Chen, Ren-Zheng Liao:
Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming. ICPADS (2) 2005: 37-41 - 2002
- [j1]Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen:
Design of a dynamic pipelined architecture for fuzzy color correction. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 924-929 (2002)
1990 – 1999
- 1999
- [c3]Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau:
A New Pipelined Architecture for Fuzzy Color Correction. ASP-DAC 1999: 209- - 1994
- [c2]Jer-Min Jou, Ren-Der Chen, Shiann-Rong Kuang:
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. ISCAS 1994: 45-48 - 1993
- [c1]Jer-Min Jou, Shiann-Rong Kuang:
Library-Adaptively Integrated Data Path Synthesis for DSP Systems. ICCD 1993: 379-382
Coauthor Index
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