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ORCIDNacer-Eddine Zergainoh
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2020 – today
- 2024
[c50]Nasr-Eddine Ouldei Tebina, Luc Salvo, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri:
Enhancing Side-Channel Attacks Through X-Ray-Induced Leakage Amplification. DATE 2024: 1-6- [c49]Nasr-Eddine Ouldei Tebina, Aghiles Douadi, Luc Salvo, Vincent Beroulle, Nacer-Eddine Zergainoh, Guillaume Hubert, Elena-Ioana Vatajelu, Giorgio Di Natale, Paolo Maistri:
Non-Invasive Attack on Ring Oscillator-Based PUFs Through Localized X-Ray Irradiation. HOST 2024: 1-11 - 2023
- [c48]Nasr-Eddine Ouldei Tebina
, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri:
Simulation Methodology for Assessing X-Ray Effects on Digital Circuits. DFT 2023: 1-6 - [c47]Nasr-Eddine Ouldei Tebina, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri:
Ray-Spect: Local Parametric Degradation for Secure Designs: An application to X-Ray Fault Injection. IOLTS 2023: 1-7 - 2022
- [c46]Nasr-Eddine Ouldei Tebina, Nacer-Eddine Zergainoh, Paolo Maistri:
X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective. DFT 2022: 1-4 - 2020
- [j17]Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis:
A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips. IEEE Trans. Emerg. Top. Comput. 8(3): 642-654 (2020)
2010 – 2019
- 2019
- [c45]Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco:
NoCFI: A Hybrid Fault Injection Method for Networks-On-Chip. LATS 2019: 1-6 - 2018
- [j16]Amir Charif, Alexandre Coelho, Masoumeh Ebrahimi, Nader Bagherzadeh, Nacer-Eddine Zergainoh:
First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip. IEEE Trans. Computers 67(10): 1430-1444 (2018) - [j15]Thierry Bonnoit, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1438-1451 (2018) - [c44]Thierry Bonnoit, Fraidy Bouesse, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution. DATE 2018: 905-908 - [c43]Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Juan A. Fraire, Raoul Velazco:
A soft-error resilient route computation unit for 3D Networks-on-Chips. DATE 2018: 1357-1362 - [c42]Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Raoul Velazco:
A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip. DFT 2018: 1-6 - 2017
- [j14]Juan A. Fraire, Pablo G. Madoery, Scott C. Burleigh, Marius Feldmann, Jorge M. Finochietto, Amir Charif, Nacer-Eddine Zergainoh, Raoul Velazco:
Assessing Contact Graph Routing Performance and Reliability in Distributed Satellite Constellations. J. Comput. Networks Commun. 2017: 2830542:1-2830542:18 (2017) - [j13]Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis:
A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips. VLSI Design 2017: 9427678:1-9427678:15 (2017) - [c41]Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU. ASP-DAC 2017: 672-677 - [c40]Amir Charif, Nacer-Eddine Zergainoh, Alexandre Coelho, Michael Nicolaidis:
Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs. ETS 2017: 1-6 - [c39]Thierry Bonnoit, Nacer-Eddine Zergainoh, Michael Nicolaidis, Raoul Velazco:
Low cost rollback to improve fault-tolerance in VLSI circuits. LASCAS 2017: 1-4 - [c38]Thierry Bonnoit, Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco:
SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core. LATS 2017: 1-4 - [c37]Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis:
MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips. LATS 2017: 1-4 - [c36]M. Solinas, Alexandre Coelho, Juan A. Fraire, Nacer-Eddine Zergainoh, Pablo A. Ferreyra, Raoul Velazco:
Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs. LATS 2017: 1-4 - 2016
- [c35]Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis:
A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs. DFT 2016: 121-126 - [c34]Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Addressing transient routing errors in fault-tolerant Networks-on-Chips. ETS 2016: 1-6 - 2015
- [c33]Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis:
MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip. IOLTS 2015: 71-76 - [c32]Vanessa Vargas, Pablo Ramos, Raoul Velazco, Jean-François Méhaut, Nacer-Eddine Zergainoh:
Evaluating SEU fault-injection on parallel applications implemented on multicore processors. LASCAS 2015: 1-4 - 2014
- [j12]Michael G. Dimopoulos, Yi Gang, Lorena Anghel, Mounir Benabdenbi, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip. Microprocess. Microsystems 38(6): 620-635 (2014) - [c31]Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis:
A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis. ETS 2014: 1-2 - [c30]Vanessa Vargas, Pablo Ramos, Wassim Mansour, Raoul Velazco, Nacer-Eddine Zergainoh, Jean-François Méhaut:
Preliminary results of SEU fault-injection on multicore processors in AMP mode. IOLTS 2014: 194-197 - 2013
- [j11]Thierry Bonnoit, Michael Nicolaidis, Nacer-Eddine Zergainoh:
Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study. J. Electron. Test. 29(3): 383-400 (2013) - [c29]Gilles Bizot, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Variability-aware and fault-tolerant self-adaptive applications for many-core chips. ETS 2013: 1 - [c28]Michael G. Dimopoulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip. IOLTS 2013: 7-12 - [c27]Gilles Bizot, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Variability-aware and fault-tolerant self-adaptive applications for many-core chips. IOLTS 2013: 37-42 - 2012
- [c26]Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky:
Design for test and reliability in ultimate CMOS. DATE 2012: 677-682 - 2011
- [j10]Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh:
On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling. J. Low Power Electron. 7(2): 265-273 (2011) - [c25]Fabien Chaix, Dimiter Avresky, Nacer-Eddine Zergainoh, Michael Nicolaidis:
A fault-tolerant deadlock-free adaptive routing for on chip interconnects. DATE 2011: 909-912 - [c24]Michael Nicolaidis, Thierry Bonnoit, Nacer-Eddine Zergainoh:
Eliminating speed penalty in ECC protected memories. DATE 2011: 1614-1619 - [c23]Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh:
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor. ETS 2011: 93-98 - [c22]Thierry Bonnoit, Michael Nicolaidis, Nacer-Eddine Zergainoh:
Towards a tool for implementing delay-free ECC in embedded memories. ICCD 2011: 441-442 - [c21]Fabien Chaix, Gilles Bizot, Michael Nicolaidis, Nacer-Eddine Zergainoh:
Variability-aware task mapping strategies for many-cores processor chips. IOLTS 2011: 55-60 - [c20]Gilles Bizot, Dimiter Avresky, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Self-Recovering Parallel Applications in Multi-core Systems. NCA 2011: 51-58 - 2010
- [c19]Fabien Chaix, Dimiter Avresky, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems. NCA 2010: 52-59 - [c18]Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh:
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS. PATMOS 2010: 94-104
2000 – 2009
- 2009
- [c17]Gilles Bizot, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Variability and reliability-aware application tasks scheduling and power control (Voltage and Frequency Scaling) in the future nanoscale multiprocessors system on chip. IOLTS 2009: 155 - 2007
- [j9]Youngchul Cho, Nacer-Eddine Zergainoh, Sungjoo Yoo, Ahmed Amine Jerraya, Kiyoung Choi:
Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip. Des. Autom. Embed. Syst. 11(2-3): 167-191 (2007) - [c16]Youssef Atat, Nacer-Eddine Zergainoh:
Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design. ISVLSI 2007: 9-14 - [c15]Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya:
Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes. IEEE International Workshop on Rapid System Prototyping 2007: 195-201 - [c14]Youngchul Cho, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi:
Buffer Size Reduction through Control-Flow Decomposition. RTCSA 2007: 183-190 - 2006
- [j8]Nacer-Eddine Zergainoh, Ludovic Tambour, Pascal Urard, Ahmed Amine Jerraya:
Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems. EURASIP J. Adv. Signal Process. 2006 (2006) - [j7]Nacer-Eddine Zergainoh, Ludovic Tambour, Ahmed Amine Jerraya:
Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 349-360 (2006) - 2005
- [j6]Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya:
Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip. Int. J. Embed. Syst. 1(1/2): 112-124 (2005) - [j5]Nacer-Eddine Zergainoh, Ludovic Tambour, Henri Michel, Ahmed Amine Jerraya:
Méthodes de correction de retard dans les modèles RTL des systèmes monopuces DSP obtenus par assemblage de composants IP : fondement théorique et implémentation. Tech. Sci. Informatiques 24(10): 1227-1257 (2005) - [c13]Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya:
Scheduler implementation in MP SoC design. ASP-DAC 2005: 151-156 - [c12]Nacer-Eddine Zergainoh, Katalin Popovici, Ahmed Amine Jerraya, Pascal Urard:
IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems. ASP-DAC 2005: 612-618 - 2004
- [j4]Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya:
A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip. Ann. des Télécommunications 59(7-8): 784-806 (2004) - 2003
- [c11]Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh:
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. DATE 2003: 20132-20137 - [c10]Ludovic Tambour, Nacer-Eddine Zergainoh, Pascal Urard, Henri Michel, Ahmed Amine Jerraya:
An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells. IEEE International Workshop on Rapid System Prototyping 2003: 56-63 - [p1]Youngchul Cho, Ganghee Lee, Kiyoung Choi, Sungjoo Yoo, Nacer-Eddine Zergainoh:
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. Embedded Software for SoC 2003: 125-136 - 2002
- [j3]Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya:
Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems. IEEE Trans. Software Eng. 28(9): 822-831 (2002) - [j2]Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya:
Exploration de l'espace des solutions architecturales dans le codesign. Tech. Sci. Informatiques 21(1): 9-35 (2002) - 2001
- [c9]Amer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya:
An efficient architecture model for systematic design of application-specific multiprocessor SoC. DATE 2001: 55-63 - 2000
- [j1]Fabiano Hessel, Pascal Coste, Philippe Le Marrec, Nacer-Eddine Zergainoh, Gabriela Nicolescu, Jean-Marc Daveau, Ahmed Amine Jerraya:
Interlanguage Communication Synthesis for Heterogeneous Specifications. Des. Autom. Embed. Syst. 5(3-4): 223-236 (2000) - [c8]Salvador Mir, Benoît Charlot, Gabriela Nicolescu, Philippe Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz:
Towards design and validation of mixed-technology SOCs. ACM Great Lakes Symposium on VLSI 2000: 29-33 - [c7]Fabiano Hessel, Philippe Coste, Gabriela Nicolescu, P. LeMarrec, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya:
Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification. ICCD 2000: 525-530 - [c6]Amer Baghdadi, Nacer-Eddine Zergainoh, Damien Lyonnard, Ahmed Amine Jerraya:
Generic Architecture Platform for Multiprocessor System-On-Chip Design. DIPES 2000: 53-64 - [c5]Nacer-Eddine Zergainoh, Amer Baghdadi, Ludovic Tambour, Damien Lyonnard, Lovic Gauthier, Ahmed Amine Jerraya:
Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip. DIPES 2000: 99-110 - [c4]Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, T. Roudier, Ahmed Amine Jerraya:
Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems. IEEE International Workshop on Rapid System Prototyping 2000: 8-13
1990 – 1999
- 1999
- [c3]Philippe Coste, Fabiano Hessel, P. LeMarrec, Zoltan Sugar, Mohamed Romdhani, Rodolph Suescun, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya:
Multilanguage design of heterogeneous systems. CODES 1999: 54-58 - [c2]Fabiano Hessel, Philippe Coste, P. LeMarrec, Nacer-Eddine Zergainoh, Jean-Marc Daveau, Ahmed Amine Jerraya:
Communication Interface Synthesis for Multilanguage Specifications. IEEE International Workshop on Rapid System Prototyping 1999: 15-20 - 1994
- [c1]Nacer-Eddine Zergainoh, Thierry Maurin, Yves Sorel, Christophe Lavarenne:
A Real Time Multiprocessor Application Development Environment Design And Implementation. PDP 1994: 544-550
Coauthor Index
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