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ORCIDSteven J. Koester
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2020 – today
- 2020
[i6]Andrew W. Stephan, Steven J. Koester:
SHE-MTJ Circuits for Convolutional Neural Networks. CoRR abs/2007.08437 (2020)- [i5]Andrew W. Stephan, Steven J. Koester:
Spin-Hall MTJ Cells for Intra-Column Competition in Hierarchical Temporal Memory. CoRR abs/2007.08659 (2020) - [i4]Andrew W. Stephan, Brian Gardner, Steven J. Koester, André Grüning:
Supervised Learning in Temporally-Coded Spiking Neural Networks with Approximate Backpropagation. CoRR abs/2007.13296 (2020)
2010 – 2019
- 2019
- [c8]V. R. Saran Kumar Chaganti
, Yao Zhang, Steven J. Koester:
Non-volatile Capacitance Tuning in Graphene/(Hf, Zr)O2/Metal Varactors. DRC 2019: 109-110 - [c7]Bingzhe Li, Jiaxi Hu, M. Hassan Najafi, Steven J. Koester, David J. Lilja:
Low Cost Hybrid Spin-CMOS Compressor for Stochastic Neural Networks. ACM Great Lakes Symposium on VLSI 2019: 141-146 - [i3]Andrew W. Stephan, Steven J. Koester:
Convolutional Neural Networks Utilizing Multifunctional Spin-Hall MTJ Neurons. CoRR abs/1905.03812 (2019) - [i2]Andrew W. Stephan, Qiuwen Lou, Michael T. Niemier, Xiaobo Sharon Hu, Steven J. Koester:
Nonvolatile Spintronic Memory Cells for Neural Networks. CoRR abs/1905.12679 (2019) - 2018
- [i1]Andrew W. Stephan, Jiaxi Hu, Steven J. Koester:
Benchmarking Inverse Rashba-Edelstein Magnetoelectric Devices for Neuromorphic Computing. CoRR abs/1811.08624 (2018) - 2017
- [c6]Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami:
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. DAC 2017: 16:1-16:6 - 2016
- [c5]Rui Ma, Qun Su, Jing Li, Steven J. Koester:
Acetone sensing using graphene quantum capacitance varactors. IEEE SENSORS 2016: 1-3 - [c4]Yao Zhang, Rui Ma, Yogish C. Kudva, Philippe Buhlmann, Steven J. Koester:
Glucose sensing with graphene varactors. IEEE SENSORS 2016: 1-3 - 2015
- [j4]Jongyeon Kim, Ayan Paul, Paul A. Crowell, Steven J. Koester, Sachin S. Sapatnekar, Jianping Wang, Chris H. Kim:
Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor. Proc. IEEE 103(1): 106-130 (2015) - 2014
- [c3]Ayan Paul, Chaitanya Kshirsagar, Sachin S. Sapatnekar, Steven J. Koester, Chris H. Kim:
Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations. VLSID 2014: 399-404 - 2013
- [j3]Yoonmyung Lee, Daeyeon Kim, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, David T. Blaauw, Dennis Sylvester:
Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs). IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1632-1643 (2013) - 2010
- [j2]Leland Chang, David J. Frank, Robert K. Montoye, Steven J. Koester, Brian L. Ji, Paul W. Coteus, Robert H. Dennard, Wilfried Haensch:
Practical Strategies for Power-Efficient Computing Technologies. Proc. IEEE 98(2): 215-236 (2010)
2000 – 2009
- 2009
- [c2]Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David T. Blaauw:
Low power circuit design based on heterojunction tunneling transistors (HETTs). ISLPED 2009: 219-224 - 2008
- [j1]Steven J. Koester, Albert M. Young, Roy R. Yu, Sampath Purushothaman, Kuan-Neng Chen, Douglas C. La Tulipe Jr., Narender Rana, Leathen Shi, Matthew R. Wordeman, Edmund J. Sprogis:
Wafer-level 3D integration technology. IBM J. Res. Dev. 52(6): 583-597 (2008) - 2007
- [c1]Kerry Bernstein, Paul S. Andry, Jerome Cann, Philip G. Emma, David Greenberg, Wilfried Haensch, Mike Ignatowski, Steven J. Koester, John Magerlein, Ruchir Puri, Albert M. Young:
Interconnects in the Third Dimension: Design Challenges for 3D ICs. DAC 2007: 562-567
Coauthor Index
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