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2020 – today
- 2023
[c35]Koichiro Ishibashi, Yuki Ogawa:
Energy Saving LED Lighting System using Illumination Beat Sensors. ICCE 2023: 1-2- 2022
- [j32]Marco Sarmiento
, Khai-Duy Nguyen, Ckristian Duran, Ronaldo Serrano, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham:
Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 69(5): 2438-2442 (2022) - [c34]Masaki Amano, Duc-Tho Mai, Guanghao Sun, Trung Nguyen Vu, Le Thi Hoi, Nguyen Thi Hoa, Koichiro Ishibashi:
Deep Learning Approach for Classifying Bacteria types using Morphology of Bacterial Colony. EMBC 2022: 2165-2168 - [c33]Tuan-Anh Tran, Koichiro Ishibashi:
High-Accuracy and Long-Range Energy Harvesting Beat Sensor with LoRa. IEEE SENSORS 2022: 1-4 - [c32]Koichiro Ishibashi:
Keynote Talk #1 RF Energy Harvesting Technology and IoT Applications. RIVF 2022: 25-26 - 2021
- [j31]Nguyen Dinh Chinh, Ha Manh Luu, Guanghao Sun, Le Quoc Anh, Pham Viet Huong, Tran Anh Vu, Tran Trong Hieu, Duc-Tan Tran, Trung Nguyen Vu, Koichiro Ishibashi, Nguyen Linh Trung:
Short time cardio-vascular pulses estimation for dengue fever screening via continuous-wave Doppler radar using empirical mode decomposition and continuous wavelet transform. Biomed. Signal Process. Control. 65: 102361 (2021) - [j30]Yuki Iwata, Han Trong Thanh, Guanghao Sun, Koichiro Ishibashi:
High Accuracy Heartbeat Detection from CW-Doppler Radar Using Singular Value Decomposition and Matched Filter. Sensors 21(11): 3588 (2021) - [j29]Marco Sarmiento, Khai-Duy Nguyen, Ckristian Duran, Trong-Thuc Hoang, Ronaldo Serrano, Van-Phuc Hoang, Xuan-Tu Tran, Koichiro Ishibashi, Cong-Kha Pham:
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3182-3186 (2021) - [c31]Duc-Tho Mai, Koichiro Ishibashi:
Bacteria Shape Classification using Small-Scale Depthwise Separable CNNs. EMBC 2021: 2940-2943 - [c30]Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Khai-Duy Nguyen, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham:
A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. ISOCC 2021: 375-376 - 2020
- [c29]Yuki Iwata, Koichiro Ishibashi, Guanghao Sun, Ha Manh Luu, Trong Thanh Han, Nguyen Linh Trung, Do Trong Tuan:
Contactless Heartbeat Detection from CW-Doppler Radar using Windowed-Singular Spectrum Analysis*. EMBC 2020: 477-480
2010 – 2019
- 2019
- [c28]Tomoyuki Ohata, Koichiro Ishibashi, Guanghao Sun:
Non-Contact Blood Pressure Measurement Scheme Using Doppler Radar. EMBC 2019: 778-781 - [c27]Kotaro Higashi, Guanghao Sun, Koichiro Ishibashi:
Precise Heart Rate Measurement Using Non-contact Doppler Radar Assisted by Machine-Learning-Based Sleep Posture Estimation. EMBC 2019: 788-791 - [c26]Koichiro Ishibashi, Ryohei Takitoge, Duangchak Manyvone, Nobuto Ono, Shigeya Yamaguchi:
Long Battery Life IoT Sensing by Beat Sensors. ICPS 2019: 430-435 - [c25]Xiaofeng Yang, Koki Kumagai, Guanghao Sun, Koichiro Ishibashi, Le Thi Hoi, Trung Nguyen Vu, Kinh Nguyen Van:
Dengue Fever Screening Using Vital Signs by Contactless Microwave Radar and Machine Learning. SAS 2019: 1-6 - 2018
- [j28]Van-Trung Nguyen, Ryo Ishikawa, Koichiro Ishibashi:
83nJ/bit Transmitter Using Code-Modulated Synchronized-OOK on 65nm SOTB for Normally-Off Wireless Sensor Networks. IEICE Trans. Electron. 101-C(7): 472-479 (2018) - [c24]Tatsuhiro Kawaguchi, Ryo Tanabe, Ryohei Takitouge, Koichiro Ishibashi, Koji Ishibashi:
Implementation of condition-aware receiver-initiated MAC protocol to realize energy-harvesting wireless sensor networks. CCNC 2018: 1-3 - [c23]Ryo Tanabe, Tatsuhiro Kawaguchi, Ryohei Takitoge, Koichiro Ishibashi, Koji Ishibashi:
Energy-aware receiver-driven medium access control protocol for wireless energy-harvesting sensor networks. CCNC 2018: 1-6 - [c22]Xiaofeng Yang, Koichiro Ishibashi, Le Hoi, Trung Nguyen Vu, Kinh Nguyen Van, Guanghao Sun:
Dengue Fever Detecting System Using Peak-detection of Data from Contactless Doppler Radar. EMBC 2018: 542-545 - [c21]Koichiro Ishibashi, Yuu Oota, Kosuke Suzuki, Ryohei Takitoge:
Plants Growth Sensing Using Beat Sensors. IEEE SENSORS 2018: 1-4 - [c20]Koichiro Ishibashi, Shiho Takahashi:
A 375 nA Input Off Current Schmitt Triger LDO for Energy Harvesting IoT Sensors. ISVLSI 2018: 187-190 - [e1]Lam-Son Lê, Tran Khanh Dang, Koichiro Ishibashi, Tran Ngoc Thinh, Cuong Pham-Quoc, Quang Tran Minh:
2018 International Conference on Advanced Computing and Applications, ACOMP 2018, Ho Chi Minh City, Vietnam, November 27-29, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-9186-1 [contents] - 2017
- [c19]Xiaofeng Yang, Koichiro Ishibashi, Toshiaki Negishi, Tetsuo Kirimoto, Guanghao Sun:
Short Time and Contactless Virus Infection Screening System with Discriminate Function Using Doppler Radar. BIC-TA 2017: 263-273 - [c18]Xiaofeng Yang, Guanghao Sun, Koichiro Ishibashi:
Non-contact acquisition of respiration and heart rates using Doppler radar with time domain peak-detection algorithm. EMBC 2017: 2847-2850 - [c17]Koichiro Ishibashi, Junya Kikuchi, Nobuyuki Sugii:
A 910nW delta sigma modulator using 65nm SOTB technology for mixed signal IC of IoT applications. ICICDT 2017: 1-3 - [c16]Ryohei Takitoge, Masataka Kishi, Koichiro Ishibashi:
Low-power enhanced temperature beat sensor with longer communication distance by data-recovery algorithm. IEEE SENSORS 2017: 1-3 - 2016
- [c15]Ryohei Takitoge, Shohei Ishigaki, Tsuyoshi Ishige, Koichiro Ishibashi:
Temperature beat: Persistent and energy harvesting wireless temperature sensing scheme. IEEE SENSORS 2016: 1-3 - 2015
- [j27]Minh-Thien Hoang, Nobuyuki Sugii, Koichiro Ishibashi:
A 27.6 µW 315 MHz low-complexity OOK receiver with on-off RF front-end. IEICE Electron. Express 12(7): 20150206 (2015) - [j26]Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham:
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. IEICE Trans. Electron. 98-C(7): 536-543 (2015) - [c14]Duc-Hung Le, Nobuyuki Sugii, Shiro Kamohara, Xuan-Thuan Nguyen, Koichiro Ishibashi, Cong-Kha Pham:
Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process. ICICDT 2015: 1-4 - 2014
- [c13]Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa:
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips 2014: 1-3 - [c12]Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham:
A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. Hot Chips Symposium 2014: 1 - 2013
- [j25]Jinmyoung Kim, Toru Nakura, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. IEICE Trans. Electron. 96-C(4): 560-567 (2013) - 2012
- [j24]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Trans. Electron. 95-C(4): 643-650 (2012) - [c11]Kazuo Otsuga, Masafumi Onouchi, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa:
An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor. SoCC 2012: 11-14 - 2011
- [j23]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Trans. Electron. 94-C(4): 511-519 (2011) - [c10]Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa:
A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process. A-SSCC 2011: 37-40 - [c9]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS 2011: 111-114 - [c8]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC 2011: 183-186 - 2010
- [j22]Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi:
A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS. IEEE J. Solid State Circuits 45(11): 2312-2320 (2010)
2000 – 2009
- 2008
- [j21]Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits 43(1): 96-108 (2008) - 2007
- [j20]Yoshihide Komatsu, Koichiro Ishibashi, Makoto Nagata:
Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias. IEICE Trans. Electron. 90-C(4): 692-698 (2007) - [j19]Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE J. Solid State Circuits 42(4): 820-829 (2007) - [c7]Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. ISSCC 2007: 488-617 - 2006
- [j18]Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada:
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. IEICE Trans. Electron. 89-C(3): 250-262 (2006) - [j17]Yoshihide Komatsu, Yukio Arima, Koichiro Ishibashi:
Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond. IEICE Trans. Electron. 89-C(3): 384-391 (2006) - 2005
- [j16]Takahiro Yamashita, Tetsuya Fujimoto, Koichiro Ishibashi:
Power Valve: for low power operation and low stand-by power. IEICE Electron. Express 2(3): 64-69 (2005) - [j15]Koichiro Ishibashi:
Special Section on Low-Power LSI and Low-Power IP. IEICE Trans. Electron. 88-C(4): 467 (2005) - [j14]Toshiro Tsukada, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada, Koichiro Ishibashi:
An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs. IEEE J. Solid State Circuits 40(1): 67-79 (2005) - [j13]Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai:
Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. Syst. Comput. Jpn. 36(6): 39-48 (2005) - [c6]Yoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata:
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. CICC 2005: 35-38 - [c5]Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD 2005: 398-405 - 2004
- [j12]Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi:
0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. IEEE J. Solid State Circuits 39(6): 934-940 (2004) - [c4]Yoshihide Komatsu, Yukio Arima, Tetsuya Fujimoto, Takahiro Yamashita, Koichiro Ishibashi:
A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond. CICC 2004: 329-332 - 2003
- [j11]Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, Koichiro Ishibashi:
16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors. IEEE J. Solid State Circuits 38(11): 1952-1957 (2003) - [c3]Hiroyuki Okada, Yasuyuki Hashimoto, Kohji Sakata, Toshiro Tsukada, Koichiro Ishibashi:
Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technology. ESSCIRC 2003: 711-714 - 2002
- [j10]Masayuki Miyazaki, Goichi Ono, Koichiro Ishibashi:
A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias. IEEE J. Solid State Circuits 37(2): 210-217 (2002) - [j9]Masanao Yamaoka, Kazumasa Yanagisawa, Shoji Shukuri, Katsuhiro Norisue, Koichiro Ishibashi:
A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit. IEEE J. Solid State Circuits 37(5): 599-604 (2002) - 2001
- [j8]Kenichi Osada, Jinuk Luke Shin, Masood Khan, Yude Liou, Karl Wang, Kenichi Shoji, Kenichi Kuroda, Shuji Ikeda, Koichiro Ishibashi:
Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell. IEEE J. Solid State Circuits 36(11): 1738-1744 (2001) - [c2]Shoji Shukuri, Kazumasa Yanagisawa, Koichiro Ishibashi:
CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip. CICC 2001: 179-182
1990 – 1999
- 1999
- [j7]Hiroyuki Mizuno, Koichiro Ishibashi, Takanori Shimura, Toshihiro Hattori, Susumu Narita, Kenji Shiozawa, Shuji Ikeda, Kunio Uchiyama:
An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode. IEEE J. Solid State Circuits 34(11): 1492-1500 (1999) - [j6]Hiroyuki Mizuno, Koichiro Ishibashi:
A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 139-144 (1999) - 1998
- [c1]Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi:
A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. ISLPED 1998: 48-53 - 1996
- [j5]Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure:
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. IEEE J. Solid State Circuits 31(11): 1618-1624 (1996) - 1995
- [j4]Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida:
A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers. IEEE J. Solid State Circuits 30(4): 480-486 (1995) - [j3]Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida:
A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. IEEE J. Solid State Circuits 30(11): 1189-1195 (1995) - 1994
- [j2]Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki:
A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers. IEEE J. Solid State Circuits 29(4): 411-418 (1994)
1980 – 1989
- 1989
- [j1]Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo:
A 9-ns 1-Mbit CMOS SRAM. IEEE J. Solid State Circuits 24(5): 1219-1225 (1989)
Coauthor Index
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