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ORCIDPrasanth Mangalagiri
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2020 – today
- 2024
[c10]Prasanth Mangalagiri, Lynn Qian, Farrukh Zafar, Praveen Mosalikanti, Phoebe Chang, Arun Kurian, Vinay Saripalli:
CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis. DAC 2024: 80:1-80:6
2010 – 2019
- 2019
- [c9]Prasanth Mangalagiri:
Analog Layout Synthesis: Are We There Yet? ISPD 2019: 127
2000 – 2009
- 2009
- [j2]Jungsub Kim, Lanping Deng, Prasanth Mangalagiri, Kevin M. Irick, Kanwaldeep Sobti, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Chaitali Chakrabarti, Nikos Pitsianis
, Xiaobai Sun:
An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization. IEEE Trans. Computers 58(12): 1654-1667 (2009) - [c8]Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijaykrishnan:
Exploiting clock skew scheduling for FPGA. DATE 2009: 1524-1529 - [c7]Prasanth Mangalagiri, Vijaykrishnan Narayanan:
Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs. ISVLSI 2009: 61-66 - 2008
- [j1]Suresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari:
Toward Increasing FPGA Lifetime. IEEE Trans. Dependable Secur. Comput. 5(2): 115-127 (2008) - [c6]Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim:
A low-power phase change memory based hybrid cache architecture. ACM Great Lakes Symposium on VLSI 2008: 395-398 - [c5]Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie, Vijaykrishnan Narayanan:
Thermal-aware reliability analysis for platform FPGAs. ICCAD 2008: 722-727 - 2007
- [c4]Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun:
TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. FPL 2007: 68-73 - [c3]Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan:
FPGA routing architecture analysis under variations. ICCD 2007: 152-157 - [c2]Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun, Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan:
Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations. SiPS 2007: 463-468 - 2006
- [c1]Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari:
FLAW: FPGA lifetime awareness. DAC 2006: 630-635
Coauthor Index
aka: Vijaykrishnan Narayanan
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