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ORCIDNagaraj Ns
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2010 – 2019
- 2010
[c6]Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Lütkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger:
Who solves the variability problem? DAC 2010: 218-219- [c5]Nagaraj Ns, John Byler, Koorosh Nazifi, Venugopal Puvvada, Toshiyuki Saito, Alan Gibbons, S. Balajee:
What's cool for the future of ultra low power designs? DAC 2010: 523-524
2000 – 2009
- 2001
- [c4]Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell:
Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. VLSI Design 2001: 365-370
1990 – 1999
- 1999
- [c3]Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano:
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. DATE 1999: 658-663 - [c2]Nagaraj Ns, Frank Cano, Sudha Thiruvengadam, Deepak Kapoor:
Performance and Reliability Verification of C6201/C6701 Digital Signal Processors. ICCD 1999: 521- - [c1]Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell:
Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. VLSI Design 1999: 6-11
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