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6th ACSAC 2001: Gold Coast, Queensland, Australia
- 6th Australasian Computer Systems Architecture Conference (ACSAC 2001), 29-30 January 2001, Gold Coast, Queensland, Australia. IEEE Computer Society 2001, ISBN 0-7695-0954-1
- Mohit Aron, Jochen Liedtke, Kevin Elphinstone, Yoonho Park, Trent Jaeger, Luke Deller:
The SawMill Framework for Virtual Memory Diversity. 3-10 - Neil W. Bergmann, Anwar S. Dawood:
Adaptive Interfacing with Reconfigurable Computers. 11-18 - David Brodrick, Anwar S. Dawood, Neil W. Bergmann, Melanie Wark:
Error Detection for Adaptive Computing Architectures in Spacecraft Applications. 19-26 - Antony Edwards, Gernot Heiser:
Components + Security = OS Extensibility. 27-34 - Kenji Watanabe, Wanming Chu, Yamin Li:
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading. 35-44 - Ernest A. Fardin, Peter Munro, Jarred Scagliotta, John Morris:
A Simulator for High Speed Digital Communications. 45-54 - K. John Gough:
Stacking them up: a Comparison of Virtual Machines. 55-61 - G. Hariprakash, R. Achutharaman, Amos Omondi:
DSTRIDE: Data-Cache Miss-Address-Based Stride Prefetching Scheme for Multimedia Processors. 62-70 - Shu-Lin Hwang, Feipei Lai:
Two Cache Lines Prediction for a Wide-Issue Micro-architecture. 71-79 - Chris R. Jesshope:
Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines. 80-88 - Heui Lee, Paul Becket, Bill Appelbe:
High-Performance Extendable Instruction Set Computing. 89-94 - Peter K. K. Loh, Heiko Schröder, Wen-Jing Hsu:
Fault-Tolerant Routing on Complete Josephus Cubes. 95-104 - Ronald Pose:
Password-Capabilities: Their Evolution from the Password-Capability System into Walnut and Beyond. 105-113 - Rajiv A. Ravindran, Rajat Moona:
Retargetable Cache Simulation Using High Level Processor Models. 114-129 - Grant B. Wigley, David A. Kearney:
The First Real Operating System for Reconfigurable Computers. 130-137 - Kunihito Yamamori, Toru Abe, Susumu Horiguchi:
Performance Evaluation of a Partial Retraining Scheme for Defective Multi-Layer Neural Networks. 138-146
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