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ORCIDJournal of Electronic Testing, Volume 11
Volume 11, Number 1, August 1997
- Vishwani D. Agrawal:
Editorial. 5 - Kwang-Ting Cheng, Kewal K. Saluja, Hans-Joachim Wunderlich:
Guest Editorial. 7-8 - Joan Carletta, Christos A. Papachristou
:
Behavioral Testability Insertion for Datapath/Controller Circuits. 9-28 - Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre:
Improving Testability of Non-Scan Designs during Behavioral Synthesis. 29-42 - Angela Krstic, Kwang-Ting Cheng:
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability. 43-54 - Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal:
Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. 55-67 - Albrecht P. Stroele:
BIST Pattern Generators Using Addition and Subtraction Operations. 69-80 - Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita:
Synthesis of Sequential Circuits by Redundancy Removal and Retiming. 81-92 - Frank F. Hsu, Janak H. Patel:
Design for Testability Using State Distances. 93-100
Volume 11, Number 2, October 1997
- Vishwani D. Agrawal:
Editorial. 107 - Marina Santo Zarnik, Franc Novak, Srecko Macek:
Design for Test of Crystal Oscillators: A Case Study. 109-117 - Hoon Chang, Jacob A. Abraham:
An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems. 119-129 - Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das:
Delay Fault Coverage Enhancement Using Variable Observation Times. 131-146 - Walter W. Weber, Adit D. Singh:
Incorporating IDDQ Testing with BIST for Improved Coverage: An Experimental Study. 147-156 - José T. de Sousa, Peter Y. K. Cheung:
Diagnosis of Boards for Realistic Interconnect Shorts. 157-171 - Bapiraju Vinnakota:
Monitoring Power Dissipation for Fault Detection. 173-181 - Jacob Savir:
Reduced Latch Count Shift Registers. 183-185 - Kevin Cattell, Jon C. Muzio:
Partial Symmetry in Cellular Automata Rule Vectors. 187-190
Volume 11, Number 3, December 1997
- Vishwani D. Agrawal:
Editorial. 195 - R. D. (Shawn) Blanton, John P. Hayes:
Testability Properties of Divergent Trees. 197-209 - Wayne H. Wolf:
Redundancy Removal during High-Level Synthesis Using Scheduling Don't-Cares. 211-225 - Peter A. Krauss, Andreas Ganz, Kurt Antreich:
Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits. 227-245 - Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck, Jamie A. Heller:
Multiple Experiment Environments for Testing. 247-262 - Rodrigue Byrne:
Determining Aliasing Probabilities in BIST by Counting Strings. 263-272 - Steven Haehn, T. S. Kalkur:
Failure Analysis of VLSI by IDDQ Testing. 273-283
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