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ORCIDIET Computers & Digital Techniques, Volume 15
Volume 15, Number 1, January 2021
- Basudev Saha
, Mukta Majumder:
An optimized knight traversal technique to detect multiple faults and Module Sequence Graph based reconfiguration of microfluidic biochip. 1-11 - L. Hemanth Krishna, Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, S. K. Noor Mahammad:
Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed multiplication. 12-19 - Udaya Shankar Santhana Krishnan, Kalpana Palanisamy:
Recycled integrated circuit detection using reliability analysis and machine learning algorithms. 20-35 - Naveen Kr. Kabra, Zuber M. Patel:
A radix-8 modulo 2n multiplier using area and power-optimized hard multiple generator. 36-55 - Vasudevan Madampu Suryasarman, Santosh Biswas, Aryabartta Sahu:
Fragmented software-based self-test technique for online intermittent fault detection in processors. 56-76
- Muhammad Rashid:
Corrigendum: Throughput/area optimised pipelined architecture for elliptic curve crypto processor. 77
Volume 15, Number 2, March 2021
- Meriam Dhouibi, Ahmed Karim Ben Salem, Afef Saidi, Slim Ben Saoud:
Accelerating Deep Neural Networks implementation: A survey. 79-96
- Celia Dharmaraj, Vinita Vasudevan, Nitin Chandrachoodan:
Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders. 97-111 - Anindita Chakraborty, Vivek Maurya, Sneha Prasad, Suryansh Gupta, Rajat Subhra Chakraborty, Hafizur Rahaman:
Binary decision diagram-based synthesis technique for improved mapping of Boolean functions inside memristive crossbar-slices. 112-124 - Geancarlo Abich, Rafael Garibotti, Vitor V. Bandeira, Felipe da Rosa, Jonas Gava, Felipe T. Bortolon, Guilherme Medeiros, Fernando Moraes, Ricardo Reis, Luciano Ost:
Evaluation of the soft error assessment consistency of a JIT-based virtual platform simulator. 125-142 - Mateus G. Silva, Guilherme L. Silvano, Ricardo O. Duarte:
RTL development of a parameterizable Reed-Solomon Codec. 143-159 - Mouna Karmani, Noura Benhadjyoussef, Belgacem Hamdi, Mohsen Machhout:
The DFA/DFT-based hacking techniques and countermeasures: Case study of the 32-bit AES encryption crypto-core. 160-170
Volume 15, Number 3, May 2021
- Bahram Rashidi:
Flexible and high-throughput structures of Camellia block cipher for security of the Internet of Things. 171-184 - Remzi Inan:
A novel FPGA-Based Bi input-reduced order extended Kalman filter for speed-sensorless direct torque control of induction motor with constant switching frequency controller. 185-201 - Marshal Raj, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko:
Reliable SRAM using NAND-NOR Gate in beyond-CMOS QCA technology. 202-213 - Heba E. Hassan, Gihan Nagib, Khaled Hosny Ibrahiem:
A novel task scheduling approach for dependent non-preemptive tasks using fuzzy logic. 214-222 - Atef Ibrahim:
Low-space bit-serial systolic array architecture for interleaved multiplication over GF(2m). 223-229
- Guilherme da Costa Ferreira, Guilherme Paim, Leandro M. G. Rocha, Gustavo M. Santana, Renato H. Neuenfeld, Eduardo A. C. da Costa, Sergio Bampi:
Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors. 230-240
Volume 15, Number 4, July 2021
- Mohammad Saeed Ansari, Shyama Gandhi, Bruce F. Cockburn, Jie Han:
Fast and low-power leading-one detectors for energy-efficient logarithmic computing. 241-250 - Pralhadrao V. Shantagiri, Rohit Kapur, Chandrasekar Shastry:
New scan compression approach to reduce the test data volume. 251-262 - Anas Razzaq, Andy Gean Ye:
Static power model for CMOS and FPGA circuits. 263-278 - Ahmad Rezaei, Ali Mahani:
Noise-based logic locking scheme against signal probability skew analysis. 279-295 - Tintu Mary John, Shanty Chacko:
FPGA-based implementation of floating point processing element for the design of efficient FIR filters. 296-301 - Yasser Ismail, Mohamed Hammad, Mahmoud Darwich, Wael Elmedany:
Homeland security video surveillance system utilising the internet of video things for smart cities. 302-319
Volume 15, Number 5, September 2021
- Xianzhong Zhou, Ying Wang:
Enhancing the security of memory in cloud infrastructure through in-phase change memory data randomisation. 321-334 - Salah Merniz, Saad Harous:
Modelling and verification of parameterized architectures: A functional approach. 335-348 - Mangal Deep Gupta, Rajeev K. Chauhan:
Coupled variable-input LCG and clock divider-based large period pseudo-random bit generator on FPGA. 349-361 - T. Nirmalraj, S. Radhakrishnan, S. K. Pandiyan:
Automatic diagnosis of single fault in interconnect testing of SRAM-based FPGA. 362-371 - Nitish Das, Aruna Priya Panchanathan:
SD-SHO: Security-dominated finite state machine state assignment technique with a satisfactory level of hardware optimization. 372-392
- Evaluation of the Soft Error Assessment Consistency of a JIT-based Virtual Platform Simulator. 393
Volume 15, Number 6, November 2021
- Saeideh Sheikhpour, Mahdi Taheri, Mohammad Saeed Ansari, Ali Mahani:
Strengthened 32-bit AES implementation: Architectural error correction configuration with a new voting scheme. 395-408 - Mickaël Fiorentino, Claude Thibeault, Yvon Savaria:
Introducing KeyRing self-timed microarchitecture and timing-driven design flow. 409-426 - Xiaoying Huang, Zhichuan Guo, Mangu Song, Xuewen Zeng:
Accelerating the SM3 hash algorithm with CPU-FPGA Co-Designed architecture. 427-436
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