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2020 – today
- 2023
[j17]Michael Pellauer
, Jason Clemons, Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Donghyuk Lee, Mike O'Connor, Anghsuman Parashar, Sean Treichler, Po-An Tsai, Stephen W. Keckler, Joel S. Emer:
Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing. ACM Trans. Comput. Syst. 41: 4:1-4:30 (2023)- 2022
- [j16]Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler:
Characterizing and Mitigating Soft Errors in GPU DRAM. IEEE Micro 42(4): 69-77 (2022) - [j15]Donghyuk Lee, Difei Wang, Xiaohong R. Yang, Jianxin Shi, Maria Teresa Landi, Bin Zhu:
SUITOR: Selecting the number of mutational signatures through cross-validation. PLoS Comput. Biol. 18(4) (2022) - [c33]Mike O'Connor, Donghyuk Lee, Niladrish Chatterjee, Michael B. Sullivan, Stephen W. Keckler:
Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings. HPCA 2022: 1001-1013 - 2021
- [j14]Yooseung Wang, Donghyuk Lee, Jiseong Heo, Jihun Park:
One-Shot Summary Prototypical Network Toward Accurate Unpaved Road Semantic Segmentation. IEEE Signal Process. Lett. 28: 1200-1204 (2021) - [c32]Atefeh Mehrabi, Donghyuk Lee, Niladrish Chatterjee, Daniel J. Sorin, Benjamin C. Lee, Mike O'Connor:
Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures. ISPASS 2021: 48-58 - [c31]Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler:
Characterizing and Mitigating Soft Errors in GPU DRAM. MICRO 2021: 641-653 - 2020
- [j13]Myeong-Ha Hwang, Ui-Kyun Na, Seungjun Lee, Byungjoo Cho, Yeri Kim, Donghyuk Lee, Jikang Shin:
MIORPA: Middleware System for Open-Source Robotic Process Automation. J. Comput. Sci. Eng. 14(1): 19-25 (2020) - [c30]Donghyuk Lee, Jinyeong Kang, Mwamba Kasongo Dahouda, Inwhee Joe, Kyungrak Lee:
DTN-SMTP: A Novel Mail Transfer Protocol with Minimized Interactions for Space Internet. ICCSA (1) 2020: 322-331
2010 – 2019
- 2019
- [j12]Donghyuk Lee, Jangmyung Lee:
A Hybrid Joystick with Impedance Control for a Stable Remote Control of a Mobile Robot. Int. J. Humanoid Robotics 16(1): 1950005:1-1950005:19 (2019) - [c29]Sangkug Lym, Donghyuk Lee, Mike O'Connor, Niladrish Chatterjee, Mattan Erez:
DeLTA: GPU Performance Model for Deep Learning Applications with In-Depth Memory System Traffic Analysis. ISPASS 2019: 293-303 - [c28]Daichi Fujiki, Niladrish Chatterjee, Donghyuk Lee, Mike O'Connor:
Near-memory data transformation for efficient sparse matrix multi-vector multiplication. SC 2019: 55:1-55:17 - [i24]Sangkug Lym, Donghyuk Lee, Mike O'Connor, Niladrish Chatterjee, Mattan Erez:
DeLTA: GPU Performance Model for Deep Learning Applications with In-depth Memory System Traffic Analysis. CoRR abs/1904.01691 (2019) - 2018
- [j11]Jeremie S. Kim, Damla Senol Cali, Hongyi Xin, Donghyuk Lee, Saugata Ghose, Mohammed Alser, Hasan Hassan, Oguz Ergin, Can Alkan, Onur Mutlu:
GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies. BMC Genom. 19(S2) (2018) - [j10]Saugata Ghose, Abdullah Giray Yaglikçi, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin K. Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, Onur Mutlu:
What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study. Proc. ACM Meas. Anal. Comput. Syst. 2(3): 38:1-38:41 (2018) - [c27]Seokyun Ryun, June Sic Kim, Donghyuk Lee, Chun Kee Chung:
Prediction of motor and somatosensory function from human ECoG. BCI 2018: 1-4 - [c26]Donghyuk Lee, Mike O'Connor, Niladrish Chatterjee:
Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction. HPCA 2018: 40-51 - [c25]Saugata Ghose, Abdullah Giray Yaglikçi, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin K. Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, Onur Mutlu:
What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study. SIGMETRICS (Abstracts) 2018: 110 - [c24]Jangmyung Lee, Hanuel Yoon, Donghyuk Lee:
A Stable Tele-operation of a Mobile Robot with the Haptic Feedback. SyRoCo 2018: 13-18 - [i23]Kevin K. Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Reducing DRAM Refresh Overheads with Refresh-Access Parallelism. CoRR abs/1805.01289 (2018) - [i22]Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu:
Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism. CoRR abs/1805.01966 (2018) - [i21]Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin K. Chang, Onur Mutlu:
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins. CoRR abs/1805.03047 (2018) - [i20]Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu:
Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost. CoRR abs/1805.03048 (2018) - [i19]Kevin K. Chang, Abhijith Kashyap, Hasan Hassan, Saugata Ghose, Kevin Hsieh, Donghyuk Lee, Tianshi Li, Gennady Pekhimenko, Samira Manabi Khan, Onur Mutlu:
Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips. CoRR abs/1805.03154 (2018) - [i18]Kevin K. Chang, Abdullah Giray Yaglikçi, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu:
Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency. CoRR abs/1805.03175 (2018) - [i17]Kevin K. Chang, Prashant J. Nair, Saugata Ghose, Donghyuk Lee, Moinuddin K. Qureshi, Onur Mutlu:
LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency. CoRR abs/1805.03184 (2018) - [i16]Hasan Hassan, Nandita Vijaykumar, Samira Manabi Khan, Saugata Ghose, Kevin K. Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, Onur Mutlu:
SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure. CoRR abs/1805.03195 (2018) - [i15]Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
RowClone: Accelerating Data Movement and Initialization Using DRAM. CoRR abs/1805.03502 (2018) - [i14]Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, Onur Mutlu:
Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency. CoRR abs/1805.03969 (2018) - [i13]Saugata Ghose, Abdullah Giray Yaglikçi, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin K. Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, Onur Mutlu:
What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study. CoRR abs/1807.05102 (2018) - 2017
- [j9]Samira Manabi Khan, Chris Wilkerson, Donghyuk Lee, Alaa R. Alameldeen, Onur Mutlu:
A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM. IEEE Comput. Archit. Lett. 16(2): 88-93 (2017) - [j8]Kevin K. Chang, Abdullah Giray Yaglikçi, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu:
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms. Proc. ACM Meas. Anal. Comput. Syst. 1(1): 10:1-10:42 (2017) - [j7]Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu:
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms. Proc. ACM Meas. Anal. Comput. Syst. 1(1): 26:1-26:36 (2017) - [c23]Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, William J. Dally:
Architecting an Energy-Efficient DRAM System for GPUs. HPCA 2017: 73-84 - [c22]Hasan Hassan, Nandita Vijaykumar, Samira Manabi Khan, Saugata Ghose, Kevin K. Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, Onur Mutlu:
SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies. HPCA 2017: 241-252 - [c21]Samira Manabi Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, Onur Mutlu:
Detecting and mitigating data-dependent DRAM failures by exploiting current memory content. MICRO 2017: 27-40 - [c20]Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson, Aditya Agrawal, Stephen W. Keckler, William J. Dally:
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems. MICRO 2017: 41-54 - [c19]Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie S. Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry:
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology. MICRO 2017: 273-287 - [c18]Kevin K. Chang, Abdullah Giray Yaglikçi, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu:
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms. SIGMETRICS (Abstracts) 2017: 52 - [c17]Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu:
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms. SIGMETRICS (Abstracts) 2017: 54 - [i12]Kevin K. Chang, Abdullah Giray Yaglikçi, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu:
Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms. CoRR abs/1705.10292 (2017) - [i11]Jeremie S. Kim, Damla Senol Cali, Hongyi Xin, Donghyuk Lee, Saugata Ghose, Mohammed Alser, Hasan Hassan, Oguz Ergin, Can Alkan, Onur Mutlu:
GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies. CoRR abs/1711.01177 (2017) - [i10]Kevin K. Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Improving DRAM Performance by Parallelizing Refreshes with Accesses. CoRR abs/1712.07754 (2017) - 2016
- [j6]Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko, Samira Manabi Khan, Onur Mutlu:
Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost. ACM Trans. Archit. Code Optim. 12(4): 63:1-63:29 (2016) - [j5]Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu:
BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling. IEEE Trans. Parallel Distributed Syst. 27(10): 3071-3087 (2016) - [c16]YoHan Park, Chang-Mo Yang, Donghyuk Lee, Choon-Woo Kim, Ho Seop Lee, Sungbum Park, Daesik Kim:
Estimation of Color Matching Functions for Tiled LCDs based on Genetic Algorithm. Color Imaging: Displaying, Processing, Hardcopy, and Applications 2016: 1-4 - [c15]Samira Manabi Khan, Donghyuk Lee, Onur Mutlu:
PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM. DSN 2016: 239-250 - [c14]Kevin K. Chang, Prashant J. Nair, Donghyuk Lee, Saugata Ghose, Moinuddin K. Qureshi, Onur Mutlu:
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM. HPCA 2016: 568-580 - [c13]Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, Onur Mutlu:
ChargeCache: Reducing DRAM latency by exploiting row access locality. HPCA 2016: 581-593 - [c12]Kevin K. Chang, Abhijith Kashyap, Hasan Hassan, Saugata Ghose, Kevin Hsieh, Donghyuk Lee, Tianshi Li, Gennady Pekhimenko, Samira Manabi Khan, Onur Mutlu:
Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization. SIGMETRICS 2016: 323-336 - [i9]Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses. CoRR abs/1601.06352 (2016) - [i8]Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu:
Tiered-Latency DRAM (TL-DRAM). CoRR abs/1601.06903 (2016) - [i7]Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu:
RowHammer: Reliability Analysis and Security Implications. CoRR abs/1603.00747 (2016) - [i6]Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu:
Adaptive-Latency DRAM (AL-DRAM). CoRR abs/1603.08454 (2016) - [i5]Donghyuk Lee:
Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity. CoRR abs/1604.08041 (2016) - [i4]Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Saugata Ghose, Onur Mutlu:
Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips. CoRR abs/1610.09604 (2016) - [i3]Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie S. Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry:
Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM. CoRR abs/1611.09988 (2016) - 2015
- [j4]Vivek Seshadri, Kevin Hsieh, Amirali Boroumand, Donghyuk Lee, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry:
Fast Bulk Bitwise AND and OR in DRAM. IEEE Comput. Archit. Lett. 14(2): 127-131 (2015) - [c11]Donghyuk Lee, Lavanya Subramanian, Rachata Ausavarungnirun, Jongmoo Choi, Onur Mutlu:
Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM. PACT 2015: 174-187 - [c10]Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu:
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case. HPCA 2015: 489-501 - [i2]Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu:
The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity. CoRR abs/1504.00390 (2015) - [i1]Donghyuk Lee, Gennady Pekhimenko, Samira Manabi Khan, Saugata Ghose, Onur Mutlu:
Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface. CoRR abs/1506.03160 (2015) - 2014
- [c9]Yunki Kim, Donghyuk Lee, Kijung Kim, Jangmyung Lee:
Improved performance of a low-cost PDR system through sensor calibration and analysis. AIM 2014: 1747-1752 - [c8]Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Improving DRAM performance by parallelizing refreshes with accesses. HPCA 2014: 356-367 - [c7]Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu:
The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost. ICCD 2014: 8-15 - [c6]Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu:
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. ISCA 2014: 361-372 - [c5]Samira Manabi Khan, Donghyuk Lee, Yoongu Kim, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu:
The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study. SIGMETRICS 2014: 519-532 - 2013
- [j3]Hongyi Xin, Donghyuk Lee, Farhad Hormozdiari, Samihan Yedkar, Onur Mutlu, Can Alkan:
Accelerating read mapping with FastHASH. BMC Genom. 14(S-1): S13 (2013) - [c4]Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu:
Tiered-latency DRAM: A low latency and low cost DRAM architecture. HPCA 2013: 615-626 - [c3]Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization. MICRO 2013: 185-197 - 2012
- [j2]Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Joo-Sun Choi, Young-Hyun Jun:
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking. IEEE J. Solid State Circuits 47(1): 107-116 (2012) - [c2]Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu:
A case for exploiting subarray-level parallelism (SALP) in DRAM. ISCA 2012: 368-379 - 2011
- [c1]Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Kyehyun Kyung, Joo-Sun Choi, Young-Hyun Jun:
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking. ISSCC 2011: 496-498
2000 – 2009
- 2008
- [j1]Jung-Sik Kim, Kyung-Woo Nam, Chi Sung Oh, Han Gu Sohn, Donghyuk Lee, Sooyoung Kim, Jong-Wook Park, Yongjun Kim, Mi-Jo Kim, Jin-Guk Kim, Hocheol Lee, Jinhyoung Kwon, Dong Il Seo, Young-Hyun Jun, Kinam Kim:
A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array. IEEE J. Solid State Circuits 43(11): 2381-2389 (2008)
Coauthor Index
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