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ORCIDLaurence Pierre
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- affiliation: IMAG, Grenoble, France
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2020 – today
- 2021
[j7]Laurence Pierre:
Refinement rules for the automatic TLM-to-RTL conversion of temporal assertions. Integr. 76: 190-204 (2021)
2010 – 2019
- 2019
- [c36]Enzo Brignon, Laurence Pierre:
Assertion-Based Verification through Binary Instrumentation. DATE 2019: 988-991 - 2018
- [c35]Martial Chabot, Laurence Pierre, Alexandre Nabais-Moreno:
Automated Testing for Cyber-physical Systems: From Scenarios to Executable Tests. FDL 2018: 5-16 - 2017
- [c34]Laurence Pierre, Martial Chabot:
Assertion-Based Verification for SoC Models and Identification of Key Events. DSD 2017: 54-61 - 2016
- [j6]Laurence Pierre:
Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements. ACM Trans. Design Autom. Electr. Syst. 21(2): 20:1-20:29 (2016) - [c33]Martial Chabot, Laurence Pierre, Alexandre Nabais-Moreno:
A requirement driven testing method for multi-disciplinary system design. MoDELS 2016: 396-405 - 2015
- [c32]Laurence Pierre:
Towards a toolchain for assertion-driven test sequence generation. FDL 2015: 82-89 - [c31]Martial Chabot, Kévin Mazet, Laurence Pierre:
Automatic and configurable instrumentation of C programs with temporal assertion checkers. MEMOCODE 2015: 208-217 - 2014
- [c30]Martial Chabot, Laurence Pierre:
A Customizable Monitoring Infrastructure for Hardware/Software Embedded Systems. ICTSS 2014: 173-179 - [c29]Zeineb Bel Hadj Amor, Laurence Pierre, Dominique Borrione:
A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow. VLSI-SoC 2014: 1-6 - 2013
- [c28]Laurence Pierre, Zeineb Bel Hadj Amor:
Automatic refinement of requirements for verification throughout the SoC design flow. CODES+ISSS 2013: 29:1-29:10 - [c27]Laurence Pierre, Fabrice Pancher, Rodolphe Suescun, Jérôme Quévremont:
On the Effectiveness of Assertion-Based Verification in an Industrial Context. FMICS 2013: 78-93 - 2012
- [c26]Laurence Pierre:
A formal framework for testing with assertion checkers in mixed-signal simulation. ICECS 2012: 284-287 - [c25]Georgios Tsiligiannis
, Laurence Pierre:
A Mixed Verification Strategy Tailored for Networks on Chip. NOCS 2012: 161-168 - [c24]Laurence Pierre, Luca Ferro, Zeineb Bel Hadj Amor, Philippe Bourgon, Jérôme Quévremont:
Integrating PSL properties into SystemC transactional modeling - Application to the verification of a modem SoC. SIES 2012: 220-228 - 2011
- [c23]Laurence Pierre, Laila Damri:
Improvement of Assertion-Based Verification through the generation of proper test sequences. FDL 2011: 1-8 - [c22]Luca Ferro, Laurence Pierre, Zeineb Bel Hadj Amor, Jérôme Lachaize, Vincent Lefftz:
Runtime Verification of Typical Requirements for a Space Critical SoC Platform. FMICS 2011: 21-36 - [c21]Renaud Clavel, Laurence Pierre, Régis Leveugle:
Towards Robustness Analysis Using PVS. ITP 2011: 71-86 - [p1]Laurence Pierre, Luca Ferro:
Dynamic Verification of SystemC Transactional Models. Model-Based Testing for Embedded Systems 2011 - 2010
- [c20]Luca Ferro, Laurence Pierre:
Formal semantics for PSL modeling layer and application to the verification of transactional models. DATE 2010: 1207-1212 - [c19]Amr Helmy, Laurence Pierre, Axel Jantsch:
Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing. DDECS 2010: 221-224 - [c18]Laurence Pierre, Luca Ferro:
Enhancing the assertion-based verification of TLM designs with reentrancy. MEMOCODE 2010: 103-112 - [c17]Vincent Lefftz, Jean Bertrand, Hugues Cassé, Christophe Clienti, Philippe Coussy, Laurent Maillet-Contoz, Philippe Mercier, Pierre Moreau, Laurence Pierre, Emmanuel Vaumorin:
A Design Flow for Critical Embedded Systems. SIES 2010: 229-233
2000 – 2009
- 2009
- [j5]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz:
A Formal Approach to the Verification of Networks on Chip. EURASIP J. Embed. Syst. 2009 (2009) - [c16]Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre:
High-level symbolic simulation for automatic model extraction. DDECS 2009: 218-221 - [c15]Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud:
Complementary Formal Approaches for Dependability Analysis. DFT 2009: 331-339 - [c14]Luca Ferro, Laurence Pierre:
ISIS: Runtime verification of TLM platforms. FDL 2009: 1-6 - 2008
- [j4]Laurence Pierre, Luca Ferro:
A Tractable and Fast Method for Monitoring SystemC TLM Specifications. IEEE Trans. Computers 57(10): 1346-1356 (2008) - [c13]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz:
Executable formal specification and validation of NoC communication infrastructures. SBCCI 2008: 176-181 - 2007
- [c12]Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz:
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. NOCS 2007: 127-136 - 2004
- [c11]Magali Contensin, Laurence Pierre:
Model-Checking Systems with Unbounded Variables without Abstraction. AMAST 2004: 87-111 - 2003
- [j3]Eric Gascard, Laurence Pierre:
Formal Proof of Applications Distributed in Symmetric Interconnection Networks. Parallel Process. Lett. 13(1): 3-18 (2003) - [c10]Magali Contensin, Laurence Pierre:
Combining ACL2 and a v-calculus Model-Checker to Verify System-Level Designs. MEMOCODE 2003: 75- - 2002
- [c9]Eric Gascard, Laurence Pierre:
Mechanical Verification of Hypercube Algorithms. IPDPS 2002 - 2001
- [c8]Eric Gascard, Laurence Pierre:
Induction-Oriented Formal Verification in Symmetric Interconnection Networks. CHARME 2001: 418-432 - 2000
- [j2]Dominique Borrione, Julia Dushina, Laurence V. Pierre:
A compositional model for the functional verification of high-level synthesis results. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 526-530 (2000)
1990 – 1999
- 1999
- [e2]Laurence Pierre, Thomas Kropf:
Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings. Lecture Notes in Computer Science 1703, Springer 1999, ISBN 3-540-66559-5 [contents] - 1998
- [c7]Dominique Borrione, Julia Dushina, Laurence Pierre:
Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis. SBCCI 1998: 99-102 - 1996
- [c6]Laurence Pierre:
Formal Specification of a Reactive System: An Exercise in VHDL, LOTOS and UNITY. ED&TC 1996: 607 - 1995
- [c5]Laurence Pierre:
Describing and verifying synchronous circuits with the Boyer-Moore theorem prover. CHARME 1995: 35-55 - 1994
- [c4]Michel Allemand, Felix Nicoli, Laurence Pierre:
Formal Verification of Hardware using LP and Comparison with Nqthm. Applied Informatics 1994: 150-153 - [c3]Felix Nicoli, Laurence Pierre:
Formal verification of behavioral VHDL specifications: a case study. EURO-DAC 1994: 560-565 - [c2]Laurence Pierre:
An Automatic Generalization Method for the Inductive Proof of Replicated and Parallel Architectures. TPCD 1994: 72-91 - 1993
- [c1]Laurence Pierre:
VHDL Description and Formal Verification of Systolic Multipliers. CHDL 1993: 225-242 - [e1]George J. Milne, Laurence Pierre:
Correct Hardware Design and Verification Methods, IFIP WG 10.5 Advanced Research Working Conference, CHARME '93, Arles, France, May 24-26, 1993, Proceedings. Lecture Notes in Computer Science 683, Springer 1993, ISBN 3-540-56778-X [contents] - 1992
- [j1]Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem:
Formal Verification of VHDL Descriptions in the Prevail Environment. IEEE Des. Test Comput. 9(2): 42-56 (1992)
Coauthor Index
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