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ORCIDLawrence T. Clark
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2020 – today
- 2022
[j35]Vinay Vashishtha
, Lawrence T. Clark:
ASAP5: A predictive PDK for the 5 nm node. Microelectron. J. 126: 105481 (2022)- [c40]Lawrence T. Clark, Alen Duvnjak, Clifford Young-Sciortino, Matthew Cannon, John S. Brunhaver, Sapan Agarwal, Jereme Neuendank, Donald Wilson, Hugh J. Barnaby, Matthew J. Marinella:
Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology. ISCAS 2022: 1205-1209 - 2021
- [j34]Vinay Vashishtha, Lawrence T. Clark:
Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node. Microelectron. J. 107: 104942 (2021)
2010 – 2019
- 2019
- [j33]Lawrence T. Clark, James Adams, Keith E. Holbert:
Reliable techniques for integrated circuit identification and true random number generation using 1.5-transistor flash memory. Integr. 65: 263-272 (2019) - [j32]Lawrence T. Clark, Sai Bharadwaj Medapuram, Divya Kiran Kadiyala, John S. Brunhaver:
Physically Unclonable Functions Using Foundry SRAM Cells. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 955-966 (2019) - [j31]John S. Brunhaver, Richard Uhrie, Lawrence T. Clark:
Itemization and Track Limitations of Fan-Out-Free Functions for Static CMOS Functional Cells. IEEE Trans. Circuits Syst. II Express Briefs 66-II(7): 1164-1168 (2019) - 2018
- [j30]Lawrence T. Clark, Sai Bharadwaj Medapuram, Divya Kiran Kadiyala:
SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 2027-2037 (2018) - 2017
- [c39]Lawrence T. Clark, Vinay Vashishtha:
Design with sub-10 nm FinFET technologies. CICC 2017: 1-87 - [c38]Vinay Vashishtha, Manoj Vangala, Lawrence T. Clark:
ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper. ICCAD 2017: 992-998 - [c37]Vinay Vashishtha, Manoj Vangala, Parv Sharma, Lawrence T. Clark:
Robust 7-nm SRAM design on a predictive PDK. ISCAS 2017: 1-4 - [c36]Vinay Vashishtha, Ankita Dosi, Lovish Masand, Lawrence T. Clark:
Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit. ISQED 2017: 149-154 - [c35]Lawrence T. Clark, James Adams, Keith E. Holbert:
Integrated circuit identification and true random numbers using 1.5-transistor flash memory. ISQED 2017: 244-249 - [c34]Lawrence T. Clark, Vinay Vashishtha, David M. Harris, Samuel Dietrich, Zunyan Wang:
Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit. MSE 2017: 1-4 - 2016
- [j29]Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric:
ASAP7: A 7-nm finFET predictive process design kit. Microelectron. J. 53: 105-115 (2016) - [j28]Lawrence T. Clark, Dan W. Patterson, Chandarasekaran Ramamurthy, Keith E. Holbert:
An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits. IEEE Trans. Computers 65(2): 382-395 (2016) - [j27]Srivatsan Chellappa, Lawrence T. Clark:
SRAM-Based Unique Chip Identifier Techniques. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1213-1222 (2016) - 2015
- [j26]José M. de la Rosa, Patrick Chiang, Lawrence T. Clark:
Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014). IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 1897-1898 (2015) - [c33]Vinay Vashishtha, Lawrence T. Clark, Srivatsan Chellappa, Anudeep R. Gogulamudi, Aditya Gujja, Chad Farnsworth:
A soft-error hardened process portable embedded microprocessor. CICC 2015: 1-4 - [c32]Sushil Kumar, Srivatsan Chellappa, Lawrence T. Clark:
Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU. ISCAS 2015: 814-817 - [c31]Aymeric Privat, Lawrence T. Clark:
Simple and accurate single event charge collection macro modeling for circuit simulation. ISCAS 2015: 1858-1861 - [c30]Vinay Vashishtha, Aditya Gujja, Lawrence T. Clark:
Delay and power tradeoffs for static and dynamic register files. ISCAS 2015: 2900-2903 - [c29]Srivatsan Chellappa, Chandarasekaran Ramamurthy, Vinay Vashishtha, Lawrence T. Clark:
Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation. ISQED 2015: 201-206 - 2014
- [c28]Lawrence T. Clark, David Kidd, Vineet Agrawal, Samuel Leshner, Gokul Krishnan:
Independent N and P process monitors for body bias based process corner correction. CICC 2014: 1-4 - [c27]Aymeric Privat, Lawrence T. Clark, Hugh J. Barnaby:
Transient response exploration of SRAM cell metastable states caused by ionizing radiation with 3D mixed mode simulation. ICECS 2014: 443-446 - [c26]Sandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark:
Methodology to optimize critical node separation in hardened flip-flops. ISQED 2014: 486-490 - [c25]Lawrence T. Clark, Sandeep Shambhulingaiah:
Methodical Design Approaches to Radiation Effects Analysis and Mitigation in Flip-Flop Circuits. ISVLSI 2014: 595-600 - 2013
- [j25]Robert Rogenmoser, Lawrence T. Clark:
Reducing Transistor Variability for High Performance Low Power Chips. IEEE Micro 33(2): 18-26 (2013) - [j24]Siddhesh S. Mhambrey, Satendra Kumar Maurya, Lawrence T. Clark:
Low Complexity Out-of-Order Issue Logic Using Static Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 380-384 (2013) - [c24]Vineet Agrawal, N. Kepler, David Kidd, Gokul Krishnan, Samuel Leshner, T. Bakishev, D. Zhao, P. Ranade, R. Roy, M. Wojko, Lawrence T. Clark, Robert Rogenmoser, M. Hori, Taiji Ema, S. Moriwaki, T. Tsuruta, T. Yamada, J. Mitani, S. Wakayama:
Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. CICC 2013: 1-4 - [c23]Lawrence T. Clark, Samuel Leshner, George Tien:
SRAM cell optimization for low AVT transistors. ISLPED 2013: 57-63 - 2011
- [j23]Satendra Kumar Maurya, Lawrence T. Clark:
A Specialized Static Content Addressable Memory for Longest Prefix Matching in Internet Protocol Routing. J. Low Power Electron. 7(3): 350-363 (2011) - [j22]Satendra Kumar Maurya, Lawrence T. Clark:
A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 963-972 (2011) - [c22]Srivatsan Chellappa, Aritra Dey, Lawrence T. Clark:
Improved circuits for microchip identification using SRAM mismatch. CICC 2011: 1-4 - [c21]Lawrence T. Clark, Tai-Hua Chen, Vikas Chaudhary:
Efficient voltage conversion for SRAM low standby power modes. ISCAS 2011: 73-76 - [c20]Lawrence T. Clark, David E. Pettit, Keith E. Holbert, Nathan D. Hindman:
Validation of and delay variation in total ionizing dose hardened standard cell libraries. ISCAS 2011: 2051-2054 - 2010
- [c19]Xiaoyin Yao, Lawrence T. Clark, Dan W. Patterson, Keith E. Holbert:
Single event transient mitigation in cache memory using transient error checking circuits. CICC 2010: 1-4 - [c18]Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark:
In-situ characterization and extraction of SRAM variability. DAC 2010: 711-716 - [c17]Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski:
Out-of-order issue logic using sorting networks. ACM Great Lakes Symposium on VLSI 2010: 385-388 - [c16]Satendra Kumar Maurya, Lawrence T. Clark:
Fast and scalable priority encoding using static CMOS. ISCAS 2010: 433-436 - [c15]Lawrence T. Clark, Vikas Chaudhary:
Fast low power translation lookaside buffers using hierarchical NAND match lines. ISCAS 2010: 3493-3496
2000 – 2009
- 2009
- [j21]Nishith N. Desai, Jonathan R. Haigh, Lawrence T. Clark:
Reducing process variation impact on replica-timed static random access memory sense timing. Integr. 42(4): 437-448 (2009) - [j20]Giby Samson, Lawrence T. Clark:
Low-Power Race-Free Programmable Logic Arrays. IEEE J. Solid State Circuits 44(3): 935-946 (2009) - [j19]Lawrence T. Clark, Anthony Chan Carusone, Payam Heydari:
Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 44(8): 2083-2084 (2009) - [c14]Satendra Kumar Maurya, Lawrence T. Clark:
Low power fast and dense longest prefix match content addressable memory for IP routers. ISLPED 2009: 389-394 - 2008
- [j18]Vikas Chaudhary, Tai-Hua Chen, F. Sheerin, Lawrence T. Clark:
Critical race-free low-power nand match line content addressable memory tagged cache memory. IET Comput. Digit. Tech. 2(1): 40-44 (2008) - [j17]Jonathan R. Haigh, Lawrence T. Clark:
High performance set associative translation lookaside buffers for low power microprocessors. Integr. 41(4): 509-523 (2008) - [j16]Sayeed A. Badrudduza, Ziyan Wang, Giby Samson, Lawrence T. Clark:
Leakage Controlled Read Stable Static Random Access Memories. J. Comput. 3(4): 39-49 (2008) - [j15]Lawrence T. Clark, Ranjit Gharpurey, Payam Heydari:
Introduction to the Special Issue on the IEEE 2007 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 43(8): 1714-1716 (2008) - [j14]Giby Samson, Nagaraj Ananthapadmanabhan, Sayeed A. Badrudduza, Lawrence T. Clark:
Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories. IEEE J. Solid State Circuits 43(11): 2524-2532 (2008) - [c13]Rahul Shringarpure, Lawrence T. Clark, Sameer M. Venugopal, David R. Allee, Shrinivas G. Uppili:
Amorphous silicon logic circuits on flexible substrates. CICC 2008: 181-184 - 2007
- [j13]Yu Cao, Lawrence T. Clark:
Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1866-1873 (2007) - [c12]Sayeed A. Badrudduza, Lawrence T. Clark:
Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability. CICC 2007: 225-228 - [c11]Lawrence T. Clark, Mohammed Kabir, Jonathan E. Knudsen:
A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity. CICC 2007: 571-574 - [c10]Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark:
LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability. VLSI Design 2007: 621-626 - 2006
- [j12]Tai-Hua Chen, Jinhui Chen, Lawrence T. Clark:
Subthreshold to Above Threshold Level Shifter Design. J. Low Power Electron. 2(2): 251-258 (2006) - [j11]Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark:
Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power. J. Low Power Electron. 2(3): 412-424 (2006) - [j10]Jinhui Chen, Lawrence T. Clark, Tai-Hua Chen:
An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage. IEEE J. Solid State Circuits 41(10): 2344-2353 (2006) - [j9]Vikas Chaudhary, Lawrence T. Clark:
Low-power high-performance nand match line content addressable memories. IEEE Trans. Very Large Scale Integr. Syst. 14(8): 895-905 (2006) - [c9]Giby Samson, Lawrence T. Clark:
A 0.13 μm Low-power Race-free Programmable Logic Array. CICC 2006: 313-316 - [c8]Giby Samson, Lawrence T. Clark:
Circuit architecture for low-power race-free programmable logic arrays. ACM Great Lakes Symposium on VLSI 2006: 416-421 - 2005
- [j8]Lawrence T. Clark, Franco Ricci, Manish Biyani:
Low standby power state storage for sub-130-nm technologies. IEEE J. Solid State Circuits 40(2): 498-506 (2005) - [j7]Jonathan R. Haigh, Michael W. Wilkerson, Jay B. Miller, Timothy S. Beatty, Stephen J. Strazdus, Lawrence T. Clark:
A low-power 2.5-GHz 90-nm level 1 cache and memory management unit. IEEE J. Solid State Circuits 40(5): 1190-1199 (2005) - [c7]Kyle R. Wissmiller, Jonathan E. Knudsen, Travis J. Alward, Zi P. Li, David R. Allee, Lawrence T. Clark:
Reducing power in flexible a-Si digital circuits while preserving state. CICC 2005: 219-222 - [c6]Yu Cao, Lawrence T. Clark:
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. DAC 2005: 658-663 - [c5]Jinhui Chen, Lawrence T. Clark, Yu Cao:
Robust Design of High Fan-In/Out Subthreshold Circuits. ICCD 2005: 405-410 - 2004
- [j6]Lawrence T. Clark, M. Morrow, W. Brown:
Reverse-body bias and supply collapse for low effective standby power. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 947-956 (2004) - [c4]Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty:
Managing standby and active mode leakage power in deep sub-micron design. ISLPED 2004: 274-279 - 2003
- [c3]Lawrence T. Clark:
Trends and challenges for wireless embedded DSPs. CICC 2003: 171-176 - [c2]Lawrence T. Clark, Byungwoo Choi, Michael W. Wilkerson:
Reducing translation lookaside buffer active power. ISLPED 2003: 10-13 - 2002
- [c1]Lawrence T. Clark, Neil Deutscher, Shay Demmons, Franco Ricci:
Standby power management for a 0.18µm microprocessor. ISLPED 2002: 7-12 - 2001
- [j5]Lawrence T. Clark, Eric J. Hoffman, Jay B. Miller, Manish Biyani, Yuyun Liao, Stephen J. Strazdus, Michael Morrow, Kimberley E. Velarde, Mark A. Yarch:
An embedded 32-b microprocessor core for low-power and high-performance applications. IEEE J. Solid State Circuits 36(11): 1599-1608 (2001)
1990 – 1999
- 1996
- [j4]Lawrence T. Clark, Gregory F. Taylor:
High fan-in circuit design. IEEE J. Solid State Circuits 31(1): 91-96 (1996) - 1994
- [j3]Robert F. Krick, Lawrence T. Clark, Daniel J. Deleganes, Keng L. Wong, Roshan Fernando, Goutam Debnath, Jashojiban Banik:
A 150 MHz 0.6 μm BiCMOS superscalar microprocessor. IEEE J. Solid State Circuits 29(12): 1455-1463 (1994) - 1990
- [j2]Arun Rao, Mark R. Walker, Lawrence T. Clark, Lex A. Akers, Robert O. Grondin:
VLSI Implementation of Neural Classifiers. Neural Comput. 2(1): 35-43 (1990)
1980 – 1989
- 1989
- [j1]Lawrence T. Clark, Robert O. Grondin:
A pipelined associated memory implemented in VLSI. IEEE J. Solid State Circuits 24(1): 28-34 (1989)
Coauthor Index
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