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ORCIDKazunori Shimizu
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2010 – 2019
- 2012
[c10]Eisuke Ito
, Kazunori Shimizu:
Frequency and Link Analysis of Online Novels Toward Social Contents Ranking. CGC 2012: 531-536- [c9]Eisuke Ito, Sachio Hirokawa, Kazunori Shimizu:
Introducing faceted views in diversity of online novels. ICDIM 2012 - [c8]Kazunori Shimizu, Shigeru Kawakami, Kouji Hayashi, Shingo Katano, Guangyuan Zhang, Dai Maekawa, Mitsuru Hashida, Satoshi Konishi:
Development of in vivo gene delivery methods in mice using tissue suction devices for abdominal endoscopic gene therapy. MHS 2012: 5-8
2000 – 2009
- 2008
- [j7]Qin Liu, Seiichiro Hiratsuka, Kazunori Shimizu, Shinsuke Ushiki, Satoshi Goto, Takeshi Ikenaga:
A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems. IEICE Trans. Electron. 91-C(4): 449-456 (2008) - [j6]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1054-1061 (2008) - [c7]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). ASP-DAC 2008: 697-702 - 2007
- [j5]Qi Wang, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto:
Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms. IEICE Trans. Electron. 90-C(10): 1964-1971 (2007) - [c6]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Power-efficient LDPC code decoder architecture. ISLPED 2007: 359-362 - 2006
- [j4]Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 969-978 (2006) - [j3]Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3602-3612 (2006) - [c5]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Memory-Efficient Accelerating Schedule for LDPC Decoder. APCCAS 2006: 1317-1320 - [c4]Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto:
High-throughput decoder for low-density parity-check code. ASP-DAC 2006: 112-113 - [c3]Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
A parallel LSI architecture for LDPC decoder improving message-passing schedule. ISCAS 2006 - 2005
- [j2]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving. IEICE Trans. Inf. Syst. 88-D(7): 1526-1537 (2005) - [c2]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Reconfigurable adaptive FEC system with interleaving. ASP-DAC 2005: 1252-1255 - [c1]Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa:
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. ICCD 2005: 503-510
1990 – 1999
- 1999
- [j1]Kazunori Shimizu, Shin-ichi Matsuoka, Nobuyuki Yamazaki, Yoshinari Oki:
High-speed End Milling of Extruded Aluminum Alloys Using Articulated Robot. J. Robotics Mechatronics 11(5): 399-403 (1999)
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