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Byung-Kwan Chun

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2020 – today

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2024
[c5]
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Wontaeck Jung, Hyunggon Kim, Do-Bin Kim, Tae-Hyun Kim, Nam-Hee Lee, Dongjin Shin, Minyoung Kim, Youngsik Rho, Hun-Jong Lee, Yujin Hyun, Jaeyoung Park, Taekyung Kim, Hwiwon Kim, Gyeongwon Lee, Jisang Lee, Joonsuc Jang, Jungmin Park, Sion Kim, Su Chang Jeon, Suyong Kim, Jung-Ho Song, Min-Seok Kim, Taesung Lee, Byung-Kwan Chun, Tongsung Kim, Young Gyu Lee, Hokil Lee, Soowoong Lee, Hwaseok Lee, Dooho Cho, Sangwan Nam, Yeomyung Kim, Kunyong Yoon, Yoonjae Lee, Sunghoon Kim, Jungseok Hwang, Raehyun Song, Hyunsik Jang, Jae-Ick Son, Hongsoo Jeon, Myunghun Lee, Mookyung Lee, Kisung Kim, Eungsuk Lee, Myeong-Woo Lee, Sungkyu Jo, Chan Ho Kim, Jong Chul Park, Kyunghwa Yun, Soonock Seol, Ji-Ho Cho, Seungjae Lee, Jin-Yub Lee, Sunghoi Hur:
13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate. ISSCC 2024: 236-237
2023
[c4]
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Youngmin Jo, Anil Kavala, Tongsung Kim, Byung-Kwan Chun, Jungjune Park, Taesung Lee, Jungmin Seo, Manjae Yang, Taehyeon Park, Hyunjin Kwon, Cheolhui Lee, Younghoon Son, Junghwan Kwak, Younggyu Lee, Hwan-Seok Ku, Dae-Hoon Na, Changyeon Yu, Jonghoon Park, Jae-Hwan Kim, Hyojin Kwon, Chan-ho Kim, Moon-Ki Jung, Chanjin Park, Donghyun Seo, Moosung Kim, Seungjae Lee, Jin-Yub Lee, Dongku Kang, Chiweon Yoon, Sunghoi Hur:
A 3.0 Gb/s/pin 4^th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package. VLSI Technology and Circuits 2023: 1-2
2021
[j4]
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Dae-Hoon Na, Jang-Woo Lee, Seon-Kyoo Lee, Hwasuk Cho, Junha Lee, Manjae Yang, Eunjin Song, Anil Kavala, Tongsung Kim, Dong-Su Jang, Youngmin Jo, Ji-Yeon Shin, Byung-Kwan Chun, Tae-Sung Lee, Byunghoon Jeong, Chiweon Yoon, Dongku Kang, Seungjae Lee, Jungdon Ihm, Dae-Seok Byeon, Jinyub Lee, Jai Hyuk Song:
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage. IEEE J. Solid State Circuits 56(4): 1129-1140 (2021)
[c3]
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Tongsung Kim, Anil Kavala, Hyunsuk Kang, Youngmin Jo, Jungjune Park, Kyoungtae Kang, Byung-Kwan Chun, Dong-Ho Shin, Dong-Su Jang, Byunghoon Jeong, Chiweon Yoon, Jinyub Lee, Jai Hyuk Song:
A Hybrid ZQ Calibration Design for High-Density Flash Memory Toggle 5.0 High-speed Interface. A-SSCC 2021: 1-2
2020
[c2]
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Jang-Woo Lee, Dae-Hoon Na, Anil Kavala, Hwasuk Cho, Junha Lee, Manjae Yang, Eunjin Song, Tongsung Kim, Seon-Kyoo Lee, Dong-Su Jang, Byung-Kwan Chun, Youngmin Jo, Sunwon Jung, Doo-Il Jung, Chan-ho Kim, Daewoon Kang, Tae-Sung Lee, Byunghoon Jeong, Chiweon Yoon, Dongku Kang, Seungjae Lee, Jungdon Ihm, Dae-Seok Byeon, Jin-Yup Lee, Sangjoon Hwang, Jai Hyuk Song:
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems. VLSI Circuits 2020: 1-2

2010 – 2019

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2014
[j3]
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Peyman Nazari, Byung-Kwan Chun, Fred Tzeng, Payam Heydari:
Polar Quantizer for Wireless Receivers: Theory, Analysis, and CMOS Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 877-887 (2014)
[j2]
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Byung-Kwan Chun, Peyman Nazari, Payam Heydari:
An SQNR Improvement Technique Based on Magnitude Segmentation for Polar Quantizers. IEEE Trans. Commun. 62(11): 3835-3841 (2014)
2011
[j1]
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Deyi Pi, Byung-Kwan Chun, Payam Heydari:
A Synthesis-Based Bandwidth Enhancement Technique for CMOS Amplifiers: Theory and Design. IEEE J. Solid State Circuits 46(2): 392-402 (2011)

2000 – 2009

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2007
[c1]
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Deyi Pi, Byung-Kwan Chun, Payam Heydari:
A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers. CICC 2007: 467-470

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