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2020 – today
- 2024
[j5]Yu-Chuan Chen, Jen-Ya Wang
:
A Lower Bound for Minimizing Waiting Time in Coexisting Virtual and Physical Worlds. IEEE Access 12: 73470-73480 (2024)- 2023
- [c7]Yeong-Yuh Xu, Pao-Sheng Yen, Yu-Hui Lin, Chung-Yu Lai, Yu-Chuan Chen, Chuan-Kang Liu:
Machine Learning-Based Outcome Prediction of Acute Ischemic Stroke After Endovascular Treatment. BCD 2023: 374-377 - 2020
- [j4]Yu-Chuan Chen, Yung-Ho Chiu, Ching-Jen Chiu:
The performance evaluation of banks considering risk: an application of undesirable relation network DEA. Int. Trans. Oper. Res. 27(2): 1101-1120 (2020) - [c6]Jau-Ji Shen, Chin-Feng Lee, Yu-Chuan Chen, Somya Agrawal:
Unsupervised Defect Detection based on Boundary Equilibrium Generative Adversarial Network. ICFET 2020: 178-182
2010 – 2019
- 2015
- [j3]Mark Po-Hung Lin, Chih-Cheng Hsu, Yu-Chuan Chen:
Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2): 280-292 (2015) - [c5]Yu-Chuan Chen, Jia-Yin Tu, Fu-Cheng Wang:
Earthquake vibration control for buildings with inerter networks. ECC 2015: 3137-3142 - [c4]Chung-Hao Lee, Yu-Chuan Chen, Fu-Cheng Wang:
Earthquake suppression for a scale building model employing inclined inerter. SII 2015: 828-833 - [c3]Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin:
Low-power gated clock tree optimization for three-dimensional integrated circuits. VLSI-DAT 2015: 1-4 - 2014
- [j2]Yu-Chuan Chen, Hyejung Ha, Hyunjoong Kim, Hongshik Ahn:
Canonical Forest. Comput. Stat. 29(3): 849-867 (2014) - 2013
- [j1]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen, Shun-Ren Siao, Shu-Hung Lin:
1-D Cell Generation With Printability Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 419-432 (2013) - [c2]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen:
Lithography-aware 1-dimensional cell generation. ECCTD 2013: 1-4 - [c1]Chih-Cheng Hsu, Yu-Chuan Chen, Mark Po-Hung Lin:
In-placement clock-tree aware multi-bit flip-flop generation for power optimization. ICCAD 2013: 592-598
Coauthor Index
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