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ORCIDRajshekar Kalayappan
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2020 – today
- 2024
[c8]C. Harshitha, Sundarapalli Harikrishna, Peddakotla Rohith, Sandeep Chandran
, Rajshekar Kalayappan:
On Decomposing Complex Test Cases for Efficient Post-silicon Validation. ASPDAC 2024: 256-261- [c7]Shruthi Karunakar, Meenakshi Atkade, Akash Poptani, Rajshekar Kalayappan, Sandeep Chandran:
CASH: Criticality-Aware Split Hybrid L1 Data Cache. ACM Great Lakes Symposium on VLSI 2024: 50-56 - [c6]Amrutha Benny, Sandeep Chandran, Rajshekar Kalayappan, Ramchandra Phawade, Piyush P. Kurur:
faRM-LTL: A Domain-Specific Architecture for Flexible and Accelerated Runtime Monitoring of LTL Properties. RV 2024: 109-127 - 2023
- [c5]Akash Poptani, Abhishek Mittal, Rishit Saiya, Rajshekar Kalayappan, Sandeep Chandran:
SANNA: Secure Acceleration of Neural Network Applications. VLSID 2023: 337-342 - [i2]Rajshekar Kalayappan, Sandeep Chandran:
Dynamic Ineffectuality-based Clustered Architectures. CoRR abs/2304.12762 (2023) - 2021
- [j8]Hadi Brais, Rajshekar Kalayappan, Preeti Ranjan Panda:
A Survey of Cache Simulators. ACM Comput. Surv. 53(1): 19:1-19:32 (2021) - [j7]Rajshekar Kalayappan, Smruti R. Sarangi:
A Formal Approach to Accountability in Heterogeneous Systems-on-Chip. IEEE Trans. Dependable Secur. Comput. 18(6): 2926-2940 (2021) - 2020
- [j6]Rajshekar Kalayappan, Avantika Chhabra, Smruti R. Sarangi:
ChunkedTejas: A Chunking-based Approach to Parallelizing a Trace-Driven Architectural Simulator. ACM Trans. Model. Comput. Simul. 30(3): 15:1-15:21 (2020)
2010 – 2019
- 2018
- [j5]Rajshekar Kalayappan, Smruti R. Sarangi:
Providing Accountability in Heterogeneous Systems-on-Chip. ACM Trans. Embed. Comput. Syst. 17(5): 83:1-83:24 (2018) - 2017
- [j4]Geetika Malhotra, Rajshekar Kalayappan, Seep Goel, Pooja Aggarwal, Abhishek Sagar, Smruti R. Sarangi:
ParTejas: A Parallel Simulator for Multicore Processors. ACM Trans. Model. Comput. Simul. 27(3): 19 (2017) - [c4]Srishty Patel, Rajshekar Kalayappan, Ishani Mahajan, Smruti R. Sarangi:
A hardware implementation of the MCAS synchronization primitive. DATE 2017: 918-921 - 2016
- [j3]Rajshekar Kalayappan, Smruti R. Sarangi:
FluidCheck: A Redundant Threading-Based Approach for Reliable Execution in Manycore Processors. ACM Trans. Archit. Code Optim. 12(4): 55:1-55:26 (2016) - [c3]Rajshekar Kalayappan, Smruti R. Sarangi:
SecCheck: A Trustworthy System with Untrusted Components. ISVLSI 2016: 379-384 - 2015
- [c2]Rajshekar Kalayappan, Smruti R. Sarangi:
SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators. ISVLSI 2015: 137-142 - [c1]Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, Eldhose Peter:
Tejas: A java based versatile micro-architectural simulator. PATMOS 2015: 47-54 - [i1]Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel:
Tejas Simulator : Validation against Hardware. CoRR abs/1501.07420 (2015) - 2014
- [j2]Amitabha Bagchi, Rajshekar Kalayappan, Surabhi Sankhla:
Surveillance using non-stealthy sensors: A new intruder model. Secur. Commun. Networks 7(11): 1900-1911 (2014) - 2013
- [j1]Rajshekar Kalayappan, Smruti R. Sarangi:
A survey of checker architectures. ACM Comput. Surv. 45(4): 48:1-48:34 (2013)
Coauthor Index
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