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ORCIDRajit Karmakar
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2020 – today
- 2022
[j6]Rajit Karmakar
, Suman Sekhar Jana, Santanu Chattopadhyay:
A Cellular Automata Guided Finite-State-Machine Watermarking Strategy for IP Protection of Sequential Circuits. IEEE Trans. Emerg. Top. Comput. 10(2): 806-823 (2022)- 2021
- [j5]Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay:
Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption. IEEE Trans. Emerg. Top. Comput. 9(4): 2109-2124 (2021) - 2020
- [j4]Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay:
A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection. Integr. 74: 93-106 (2020) - [j3]Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur:
A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 546-550 (2020) - [c15]Rajit Karmakar, Santanu Chattopadhyay:
A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking in The Absence of Scan Access. DATE 2020: 448-453 - [c14]Rajit Karmakar, Santanu Chattopadhyay:
On Securing Scan Obfuscation Strategies Against ScanSAT Attack. ISQED 2020: 213-218 - [c13]Rajit Karmakar, Santanu Chattopadhyay:
Hardware IP Protection Using Logic Encryption and Watermarking. ITC 2020: 1-10
2010 – 2019
- 2019
- [c12]Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay:
A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis. DAC 2019: 90 - [c11]Rajit Karmakar, Santanu Chattopadhyay, Mrityunjoy Chakraborty:
Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure. ISCAS 2019: 1-5 - 2018
- [c10]Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay:
On Finding Suitable Key-Gate Locations In Logic Encryption. ISCAS 2018: 1-5 - [i1]Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur:
Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits. CoRR abs/1801.04961 (2018) - 2017
- [j2]Rajit Karmakar, Santanu Chattopadhyay:
Temperature and data size trade-off in dictionary based test data compression. Integr. 57: 20-33 (2017) - [c9]N. Prasad, Rajit Karmakar, Santanu Chattopadhyay, Indrajit Chakrabarti:
Runtime mitigation of illegal packet request attacks in Networks-on-Chip. ISCAS 2017: 1-4 - [c8]Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur:
Enhancing security of logic encryption using embedded key generation unit. ITC-Asia 2017: 131-136 - [c7]Rajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta:
A New Logic Encryption Strategy Ensuring Key Interdependency. VLSID 2017: 429-434 - 2016
- [c6]Rajit Karmakar, Santanu Chattopadhyay:
Thermal-Safe Schedule Generation for System-on-Chip Testing. VLSID 2016: 475-480 - [c5]Srinivasa Shashank Nuthakki, Rajit Karmakar, Santanu Chattopadhyay, Krishnendu Chakrabarty:
Optimization of the IEEE 1687 access network for hybrid access schedules. VTS 2016: 1-6 - 2015
- [j1]Rajit Karmakar, Santanu Chattopadhyay:
Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling. Integr. 50: 61-73 (2015) - [c4]Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay:
Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints. ATS 2015: 73-78 - [c3]Rajit Karmakar, Santanu Chattopadhyay:
Thermal-Aware Test Data Compression Using Dictionary Based Coding. VLSID 2015: 53-58 - [c2]Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay:
Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach. VTS 2015: 1-6 - 2014
- [c1]Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay:
Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model. VDAT 2014: 1-6
Coauthor Index
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