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ORCIDBrett H. Meyer
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2020 – today
- 2024
[c51]Hang Zhang, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross:
Intermediate Layer Distillation with the Reused Teacher Classifier: A Study on the Importance of the Classifier of Attention-based Models. EMNLP (Findings) 2024: 7203-7212- [i15]Lulan Shen, Ali Edalati, Brett H. Meyer, Warren J. Gross, James J. Clark:
Robustness to distribution shifts of compressed networks for edge devices. CoRR abs/2401.12014 (2024) - [i14]Lulan Shen, Ali Edalati, Brett H. Meyer, Warren J. Gross, James J. Clark:
AdCorDA: Classifier Refinement via Adversarial Correction and Domain Adaptation. CoRR abs/2401.13212 (2024) - [i13]Mohammadreza Tayaranian, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross:
Faster Inference of Integer SWIN Transformer by Removing the GELU Activation. CoRR abs/2402.01169 (2024) - [i12]Mohammadreza Tayaranian, Seyyed Hasan Mozafari, Brett H. Meyer, James J. Clark, Warren J. Gross:
Automatic Pruning of Fine-tuning Datasets for Transformer-based Language Models. CoRR abs/2407.08887 (2024) - 2023
- [j23]Jarul Mehta
, Guillaume Richard, Loren Lugosch, Derek Yu, Brett H. Meyer:
DT-DS: CAN Intrusion Detection with Decision Tree Ensembles. ACM Trans. Cyber Phys. Syst. 7(1): 4:1-4:27 (2023) - [j22]Hung-Yang Chang, Seyyed Hasan Mozafari, Cheng Chen, James J. Clark, Brett H. Meyer, Warren J. Gross:
PipeBERT: High-throughput BERT Inference for ARM Big.LITTLE Multi-core Processors. J. Signal Process. Syst. 95(7): 877-894 (2023) - [c50]Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer:
Efficient 1D Grouped Convolution for PyTorch a Case Study: Fast On-Device Fine-Tuning for SqueezeBERT. ASAP 2023: 69-75 - [c49]Lulan Shen, Ibtihel Amara, Ruofeng Li, Brett H. Meyer, Warren J. Gross, James J. Clark:
Fast Fine-Tuning Using Curriculum Domain Adaptation. CRV 2023: 296-303 - [c48]Hung-Yang Chang, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross:
High-Throughput Edge Inference for BERT Models via Neural Architecture Search and Pipeline. ACM Great Lakes Symposium on VLSI 2023: 455-459 - [c47]Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer:
Training Acceleration of Frequency Domain CNNs Using Activation Compression. ISCAS 2023: 1-5 - [i11]Zhuoran Xiong, Marihan Amein, Olivier Therrien, Warren J. Gross, Brett H. Meyer:
FMAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation. CoRR abs/2303.16322 (2023) - [i10]Olivier Therrien, Marihan Amein, Zhuoran Xiong, Warren J. Gross, Brett H. Meyer:
SSS3D: Fast Neural Architecture Search For Efficient Three-Dimensional Semantic Segmentation. CoRR abs/2304.11207 (2023) - 2022
- [c46]Murray L. Kornelsen, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross:
Fast Heterogeneous Task Mapping for Reducing Edge DNN Latency. ASAP 2022: 64-71 - [c45]Marihan Amein, Zhuoran Xiong, Olivier Therrien, Brett H. Meyer, Warren J. Gross:
Work-in-Progress: SuperNAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation. CASES 2022: 35-36 - [c44]Negin Firouzian, Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer:
Work-in-Progress: Utilizing latency and accuracy predictors for efficient hardware-aware NAS. CODES+ISSS 2022: 15-16 - [c43]Lulan Shen, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark:
Conjugate Adder Net (CAddNet) - a Space-Efficient Approximate CNN. CVPR Workshops 2022: 2792-2796 - [c42]Ibtihel Amara, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark:
CES-KD: Curriculum-based Expert Selection for Guided Knowledge Distillation. ICPR 2022: 1901-1907 - [c41]Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross:
Efficient Fine-Tuning of BERT Models on the Edge. ISCAS 2022: 1838-1842 - [c40]M. Abdelgawad, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross:
BERTPerf: Inference Latency Predictor for BERT on ARM big.LITTLE Multi-Core Processors. SiPS 2022: 1-6 - [i9]Amir Ardakani, Arash Ardakani, Brett H. Meyer, James J. Clark, Warren J. Gross:
Standard Deviation-Based Quantization for Deep Neural Networks. CoRR abs/2202.12422 (2022) - [i8]Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross:
Efficient Fine-Tuning of BERT Models on the Edge. CoRR abs/2205.01541 (2022) - [i7]Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross:
Efficient Fine-Tuning of Compressed Language Models with Learners. CoRR abs/2208.02070 (2022) - [i6]Ibtihel Amara, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark:
CES-KD: Curriculum-based Expert Selection for Guided Knowledge Distillation. CoRR abs/2209.07606 (2022) - [i5]Ibtihel Amara, Nazanin Mohammadi Sepahvand, Brett H. Meyer, Warren J. Gross, James J. Clark:
BD-KD: Balancing the Divergences for Online Knowledge Distillation. CoRR abs/2212.12965 (2022) - 2021
- [j21]Warren J. Gross, Brett H. Meyer, Arash Ardakani:
Hardware-Aware Design for Edge Intelligence. IEEE Open J. Circuits Syst. 2: 113-127 (2021) - [j20]Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer:
Implementing Convolutional Neural Networks Using Hartley Stochastic Computing With Adaptive Rate Feature Map Compression. IEEE Open J. Circuits Syst. 2: 805-819 (2021) - [j19]Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
A Design Framework for Invertible Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 655-665 (2021) - [j18]Márton Búr, Kristóf Marussy, Brett H. Meyer, Dániel Varró:
Worst-case Execution Time Calculation for Query-based Monitors by Witness Generation. ACM Trans. Embed. Comput. Syst. 20(6): 107:1-107:36 (2021) - [c39]Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer:
Hartley Stochastic Computing For Convolutional Neural Networks. SiPS 2021: 1-6 - [i4]Márton Búr, Kristóf Marussy, Brett H. Meyer, Dániel Varró:
Worst-Case Execution Time Calculation for Query-Based Monitors by Witness Generation. CoRR abs/2102.03116 (2021) - 2020
- [j17]Seyyed Hasan Mozafari, Brett H. Meyer:
Hot sparing for lifetime-chip-performance and cost improvement in application specific SIMT processors. Des. Autom. Embed. Syst. 24(4): 249-266 (2020) - [j16]Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu:
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1541-1550 (2020) - [c38]Zixuan Yin, Warren J. Gross, Brett H. Meyer:
Probabilistic Sequential Multi-Objective Optimization of Convolutional Neural Networks. DATE 2020: 1055-1060 - [c37]Loren Lugosch, Brett H. Meyer, Derek Nowrouzezahrai, Mirco Ravanelli:
Using Speech Synthesis to Train End-To-End Spoken Language Understanding Models. ICASSP 2020: 8499-8503 - [i3]Loren Lugosch, Derek Nowrouzezahrai, Brett H. Meyer:
Surprisal-Triggered Conditional Computation with Neural Networks. CoRR abs/2006.01659 (2020)
2010 – 2019
- 2019
- [j15]Seyyed Hasan Mozafari, Brett H. Meyer:
Characterizing the Effectiveness of Hot Sparing on Cost and Performance-per-Watt in Application Specific SIMT. Integr. 69: 198-209 (2019) - [j14]Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu:
Efficient CMOS Invertible Logic Using Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2263-2274 (2019) - [j13]Zaid Al-bayati, Youcheng Sun, Haibo Zeng, Marco Di Natale, Qi Zhu, Brett H. Meyer:
Partitioning and Selection of Data Consistency Mechanisms for Multicore Real-Time Systems. ACM Trans. Embed. Comput. Syst. 18(4): 35:1-35:28 (2019) - [c36]Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
A Design Framework for Invertible Logic. ACSSC 2019: 312-316 - [c35]Arash Ardakani, Zhengyun Ji, Sean C. Smithson, Brett H. Meyer, Warren J. Gross:
Learning Recurrent Binary/Ternary Weights. ICLR (Poster) 2019 - [c34]Derek Yu, Michael Vaquier, Evan Laflamme, Gabrielle Doucette-Poirier, Justin Tremblay, Brett H. Meyer:
ARINC-825TBv2: A Hardware-in-the-Ioop Simulation Platform for Aerospace Security Research. RSP 2019: 29-35 - 2018
- [j12]Jonah Caplan, Zaid Al-bayati, Haibo Zeng, Brett H. Meyer:
Mapping and Scheduling Mixed-Criticality Systems with On-Demand Redundancy. IEEE Trans. Computers 67(4): 582-588 (2018) - [j11]Seyyed Hasan Mozafari, Brett H. Meyer:
Efficient Performance Evaluation of Multi-Core SIMT Processors with Hot Redundancy. IEEE Trans. Emerg. Top. Comput. 6(4): 498-510 (2018) - [c33]Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
Study of Stochastic Invertible Multiplier Designs. ICECS 2018: 649-650 - [i2]Arash Ardakani, Zhengyun Ji, Sean C. Smithson, Brett H. Meyer, Warren J. Gross:
Learning Recurrent Binary/Ternary Weights. CoRR abs/1809.11086 (2018) - 2017
- [j10]Maria Isabel Mera, Jonah Caplan, Seyyed Hasan Mozafari, Brett H. Meyer, Peter A. Milder:
Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression. ACM Trans. Embed. Comput. Syst. 16(4): 96:1-96:20 (2017) - [c32]Calvin Ma, Aditya Mahajan, Brett H. Meyer:
Multi-armed bandits for efficient lifetime estimation in MPSoC design. DATE 2017: 1540-1545 - 2016
- [j9]Runjie Zhang, Brett H. Meyer, Ke Wang, Mircea R. Stan, Kevin Skadron:
Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2335-2344 (2016) - [c31]Zaid Al-bayati, Jonah Caplan, Brett H. Meyer, Haibo Zeng:
A four-mode model for efficient fault-tolerant mixed-criticality systems. DATE 2016: 97-102 - [c30]Mojing Liu, Brett H. Meyer:
Bounding error detection latency in safety critical systems with enhanced Execution Fingerprinting. DFT 2016: 47-52 - [c29]Zaid Al-bayati, Brett H. Meyer, Haibo Zeng:
Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures. DFT 2016: 57-62 - [c28]Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic:
Capturing True Workload Dependency of BTI-induced Degradation in CPU Components. ACM Great Lakes Symposium on VLSI 2016: 373-376 - [c27]Sean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer:
Neural networks designing neural networks: multi-objective hyper-parameter optimization. ICCAD 2016: 104 - [c26]Scott Dickson Dagondon, Warren J. Gross, Brett H. Meyer:
Sparse-Clustered Network with Selective Decoding for Internet Traffic Classification. SiPS 2016: 177-182 - [c25]Sean C. Smithson, Kaushik Boga, Arash Ardakani, Brett H. Meyer, Warren J. Gross:
Stochastic Computing Can Improve Upon Digital Spiking Neural Networks. SiPS 2016: 309-314 - [i1]Sean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer:
Neural Networks Designing Neural Networks: Multi-Objective Hyper-Parameter Optimization. CoRR abs/1611.02120 (2016) - 2015
- [j8]Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer:
Techniques for on-demand structural redundancy for massively parallel processor arrays. J. Syst. Archit. 61(10): 615-627 (2015) - [c24]Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer:
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS 2015: 1-8 - [c23]Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea R. Stan:
A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC. DAC 2015: 133:1-133:6 - [c22]Badrun Nahar, Brett H. Meyer:
RotR: Rotational redundant task mapping for fail-operational MPSoCs. DFTS 2015: 21-28 - [c21]Seyyed Hasan Mozafari, Brett H. Meyer:
Hot spare components for performance-cost improvement in multi-core SIMT. DFTS 2015: 53-59 - [c20]Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic:
Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models. ACM Great Lakes Symposium on VLSI 2015: 57-62 - [c19]Seyyed Hasan Mozafari, Brett H. Meyer, Kevin Skadron:
Yield-aware Performance-Cost Characterization for Multi-Core SIMT. ACM Great Lakes Symposium on VLSI 2015: 237-240 - [c18]Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea R. Stan:
Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC. ISLPED 2015: 152-158 - [c17]Zaid Al-bayati, Youcheng Sun, Haibo Zeng, Marco Di Natale, Qi Zhu, Brett H. Meyer:
Task placement and selection of data consistency mechanisms for real-time multicore applications. RTAS 2015: 172-181 - 2014
- [j7]Brett H. Meyer, Adam S. Hartman, Donald E. Thomas:
Cost-effective lifetime and yield optimization for NoC-based MPSoCs. ACM Trans. Design Autom. Electr. Syst. 19(2): 12:1-12:33 (2014) - [c16]Ke Wang, Brett H. Meyer, Runjie Zhang, Kevin Skadron, Mircea R. Stan:
Walking pads: Fast power-supply pad-placement optimization. ASP-DAC 2014: 537-543 - [c15]Ke Wang, Brett H. Meyer, Runjie Zhang, Mircea R. Stan, Kevin Skadron:
Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization. DAC 2014: 126:1-126:6 - [c14]Jonah Caplan, Maria Isabel Mera, Peter A. Milder, Brett H. Meyer:
Trade-offs in execution signature compression for reliable processor systems. DATE 2014: 1-6 - [c13]Saad Arrabi, D. Moore, L. Wang, Kevin Skadron, Benton H. Calhoun, John C. Lach, Brett H. Meyer:
Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems. FCCM 2014: 236 - [c12]Chen Jiang, Mojing Liu, Brett H. Meyer:
MB-FICA: multi-bit fault injection and coverage analysis. ACM Great Lakes Symposium on VLSI 2014: 205-210 - [c11]Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Zeljko Zilic:
Linear regression techniques for efficient analysis of transistor variability. ICECS 2014: 267-270 - [c10]Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron:
Architecture implications of pads as a scarce resource. ISCA 2014: 373-384 - 2013
- [j6]Karthik Sankaranarayanan, Brett H. Meyer, Wei Huang, Robert J. Ribando, Hossein Haj-Hariri, Mircea R. Stan, Kevin Skadron:
Architectural implications of spatial thermal filtering. Integr. 46(1): 44-56 (2013) - [j5]Lukasz G. Szafaryn, Brett H. Meyer, Kevin Skadron:
Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core. IEEE Micro 33(4): 56-65 (2013) - 2012
- [c9]Gregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan, Brett H. Meyer:
ArchFP: Rapid prototyping of pre-RTL floorplans. VLSI-SoC 2012: 183-188 - 2011
- [j4]Karthik Sankaranarayanan, Brett H. Meyer, Mircea R. Stan, Kevin Skadron:
Thermal benefit of multi-core floorplanning: A limits study. Sustain. Comput. Informatics Syst. 1(4): 286-293 (2011) - [c8]Brett H. Meyer, Benton H. Calhoun, John C. Lach, Kevin Skadron:
Cost-effective safety and fault localization using distributed temporal redundancy. CASES 2011: 125-134 - [c7]Brett H. Meyer, Nishant J. George, Benton H. Calhoun, John C. Lach, Kevin Skadron:
Reducing the cost of redundant execution in safety-critical systems using relaxed dedication. DATE 2011: 1249-1254 - 2010
- [c6]Adam S. Hartman, Donald E. Thomas, Brett H. Meyer:
A case for lifetime-aware task mapping in embedded chip multiprocessors. CODES+ISSS 2010: 145-154 - [c5]Brett H. Meyer, Adam S. Hartman, Donald E. Thomas:
Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs. DATE 2010: 1596-1601 - [c4]Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron, Mircea R. Stan:
Temperature-to-power mapping. ICCD 2010: 384-389 - [c3]Brett H. Meyer, Adam S. Hartman, Donald E. Thomas:
Slack allocation for yield improvement in NoC-based MPSoCs. ISQED 2010: 738-746
2000 – 2009
- 2009
- [j3]Brett H. Meyer, Donald E. Thomas:
Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC. Des. Autom. Embed. Syst. 13(1-2): 73-88 (2009) - 2007
- [j2]JoAnn M. Paul, Brett H. Meyer:
Amdahl's Law Revisited for Single Chip Systems. Int. J. Parallel Program. 35(2): 101-123 (2007) - [c2]Brett H. Meyer, Donald E. Thomas:
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. CODES+ISSS 2007: 3-8 - [c1]Brett H. Meyer, Donald E. Thomas:
Rethinking Automated Synthesis of MPSoC Architectures. IPDPS 2007: 1-6 - 2005
- [j1]Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffrey E. Nelson, Sean M. Pieper, Anthony G. Rowe:
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors. IEEE Trans. Computers 54(6): 684-697 (2005)
Coauthor Index
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