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ORCIDGururaj Saileshwar
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2020 – today
- 2024
[c19]Aamer Jaleel, Gururaj Saileshwar, Stephen W. Keckler, Moinuddin K. Qureshi:
PrIDE: Achieving Secure Rowhammer Mitigation with Low-Cost In-DRAM Trackers. ISCA 2024: 1157-1172- [i6]Aamer Jaleel, Stephen W. Keckler, Gururaj Saileshwar:
Probabilistic Tracker Management Policies for Low-Cost and Scalable Rowhammer Mitigation. CoRR abs/2404.16256 (2024) - 2023
- [j3]Anurag Kar
, Xueyang Liu, Yonghae Kim, Gururaj Saileshwar, Hyesoon Kim, Tushar Krishna:
Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping. IEEE Comput. Archit. Lett. 22(1): 53-56 (2023) - [j2]Gururaj Saileshwar, Moinuddin K. Qureshi:
The Mirage of Breaking MIRAGE: Analyzing the Modeling Pitfalls in Emerging "Attacks" on MIRAGE. IEEE Comput. Archit. Lett. 22(2): 121-124 (2023) - [c18]Anish Saxena, Gururaj Saileshwar, Jonas Juffinger, Andreas Kogler, Daniel Gruss, Moinuddin K. Qureshi:
PT-Guard: Integrity-Protected Page Tables to Defend Against Breakthrough Rowhammer Attacks. DSN 2023: 95-108 - [c17]Jeonghyun Woo, Gururaj Saileshwar, Prashant J. Nair:
Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems. HPCA 2023: 374-389 - [c16]Martin Schwarzl, Pietro Borrello, Gururaj Saileshwar, Hanna Müller, Michael Schwarz, Daniel Gruss:
Practical Timing Side-Channel Attacks on Memory Compression. SP 2023: 1186-1203 - [c15]Stefan Gast, Jonas Juffinger, Martin Schwarzl, Gururaj Saileshwar, Andreas Kogler, Simone Franza, Markus Köstl, Daniel Gruss:
SQUIP: Exploiting the Scheduler Queue Contention Side Channel. SP 2023: 2256-2272 - [i5]Gururaj Saileshwar, Moinuddin K. Qureshi:
The Mirage of Breaking MIRAGE: Refuting the HPCA-2023 Paper "Are Randomized Caches Truly Random?". CoRR abs/2303.15673 (2023) - 2022
- [b1]Gururaj Saileshwar:
Architecting Secure Processor Caches. Georgia Institute of Technology, Atlanta, GA, USA, 2022 - [j1]Gururaj Saileshwar, Rick Boivie, Tong Chen, Benjamin Segal, Alper Buyuktosunoglu:
HeapCheck: Low-cost Hardware Support for Memory Safety. ACM Trans. Archit. Code Optim. 19(1): 10:1-10:24 (2022) - [c14]Gururaj Saileshwar, Bolin Wang, Moinuddin K. Qureshi, Prashant J. Nair:
Randomized row-swap: mitigating Row Hammer by breaking spatial correlation between aggressor and victim rows. ASPLOS 2022: 1056-1069 - [c13]Rick Boivie, Gururaj Saileshwar, Tong Chen, Benjamin Segal, Alper Buyuktosunoglu:
On the Scalability of HeapCheck. DSN (Supplements) 2022: 15-18 - [c12]Moinuddin K. Qureshi, Aditya Rohan, Gururaj Saileshwar, Prashant J. Nair:
Hydra: enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking. ISCA 2022: 699-710 - [c11]Anish Saxena, Gururaj Saileshwar, Prashant J. Nair, Moinuddin K. Qureshi:
AQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime. MICRO 2022: 108-123 - [i4]Jeonghyun Woo, Gururaj Saileshwar, Prashant J. Nair:
Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems. CoRR abs/2212.12613 (2022) - 2021
- [c10]Gururaj Saileshwar, Christopher W. Fletcher, Moinuddin K. Qureshi:
Streamline: a fast, flushless cache covert-channel attack by enabling asynchronous collusion. ASPLOS 2021: 1077-1090 - [c9]Ren Ding, Yonghae Kim, Fan Sang, Wen Xu, Gururaj Saileshwar, Taesoo Kim:
Hardware Support to Improve Fuzzing Performance and Precision. CCS 2021: 2214-2228 - [c8]Rick Boivie, Gururaj Saileshwar, Tong Chen, Benjamin Segal, Alper Buyuktosunoglu:
Hardware Support for Low-Cost Memory Safety. DSN (Supplements) 2021: 57-60 - [c7]Gururaj Saileshwar, Sanjay Kariyappa, Moinuddin K. Qureshi:
Bespoke Cache Enclaves: Fine-Grained and Scalable Isolation from Cache Side-Channels via Flexible Set-Partitioning. SEED 2021: 37-49 - [c6]Gururaj Saileshwar, Moinuddin K. Qureshi:
MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design. USENIX Security Symposium 2021: 1379-1396 - [c5]Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, Abdulrahman Mahmoud, Saugata Ghose, Joel S. Emer:
Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future. WCAE 2021: 1-9 - [i3]Martin Schwarzl, Pietro Borrello, Gururaj Saileshwar, Hanna Müller, Michael Schwarz, Daniel Gruss:
Practical Timing Side Channel Attacks on Memory Compression. CoRR abs/2111.08404 (2021) - 2020
- [i2]Gururaj Saileshwar, Moinuddin K. Qureshi:
MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design. CoRR abs/2009.09090 (2020)
2010 – 2019
- 2019
- [c4]Gururaj Saileshwar, Moinuddin K. Qureshi:
CleanupSpec: An "Undo" Approach to Safe Speculation. MICRO 2019: 73-86 - [i1]Gururaj Saileshwar, Moinuddin K. Qureshi:
Lookout for Zombies: Mitigating Flush+Reload Attack on Shared Caches by Monitoring Invalidated Lines. CoRR abs/1906.02362 (2019) - 2018
- [c3]Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Moinuddin K. Qureshi:
SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories. HPCA 2018: 454-465 - [c2]Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, José A. Joao, Moinuddin K. Qureshi:
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories. MICRO 2018: 416-427 - 2011
- [c1]Priyanka Kabara, Sanket Thakur, Gururaj Saileshwar, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
CMOS low-noise signal conditioning with a novel differential "resistance to frequency" converter for resistive sensor applications. ISOCC 2011: 298-301
Coauthor Index
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last updated on 2024-11-15 19:35 CET by the dblp team
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