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ORCIDMathias Soeken
Person information
- affiliation: Microsoft Quantum, Switzerland
- affiliation (former): EPFL, Lausanne, Switzerland
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2020 – today
- 2023
[c139]Wim van Dam
, Mariia Mykhailova, Mathias Soeken:
Using Azure Quantum Resource Estimator for Assessing Performance of Fault Tolerant Quantum Computation. SC Workshops 2023: 1412-1419- 2022
- [j28]Jie-Hong R. Jiang, Giovanni De Micheli, Kaitlin N. Smith, Mathias Soeken:
Design and Automation for Quantum Computation and Quantum Technologies. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(3): 581-583 (2022) - [j27]Giovanni De Micheli, Jie-Hong R. Jiang, Robert Rand, Kaitlin N. Smith, Mathias Soeken:
Advances in Quantum Computation and Quantum Technologies: A Design Automation Perspective. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(3): 584-601 (2022) - [c138]Mathias Soeken, Mariia Mykhailova:
Automatic oracle generation in microsoft's quantum development kit using QIR and LLVM passes. DAC 2022: 1363-1366 - [i26]Thomas Häner, Mathias Soeken:
The multiplicative complexity of interval checking. CoRR abs/2201.10200 (2022) - [i25]Thomas Häner, Vadym Kliuchnikov, Martin Roetteler, Mathias Soeken, Alexander Vaschillo:
QParallel: Explicit Parallelism for Programming Quantum Computers. CoRR abs/2210.03680 (2022) - [i24]Rajiv Krishnakumar, Mathias Soeken, Martin Roetteler, William J. Zeng:
A Q# Implementation of a Quantum Lookup Table for Quantum Arithmetic Functions. CoRR abs/2210.11786 (2022) - [i23]Thomas Häner, Vadym Kliuchnikov, Martin Roetteler, Mathias Soeken:
Space-time optimized table lookup. CoRR abs/2211.01133 (2022) - [i22]Michael E. Beverland, Prakash Murali, Matthias Troyer, Krysta M. Svore, Torsten Hoefler, Vadym Kliuchnikov, Guang Hao Low, Mathias Soeken, Aarthi Sundaram, Alexander Vaschillo:
Assessing requirements to scale to practical quantum advantage. CoRR abs/2211.07629 (2022) - [i21]Thomas Häner, Mathias Soeken:
The multiplicative complexity of interval checking. IACR Cryptol. ePrint Arch. 2022: 91 (2022) - 2021
- [j26]Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli:
Three-Input Gates for Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2184-2188 (2021) - [c137]Mathias Soeken, Mariia Mykhailova, Vadym Kliuchnikov, Christopher E. Granade, Alexander Vaschillo:
A Resource Estimation and Verification Workflow in Q# Special session paper. DATE 2021: 1050-1055 - [c136]Mariia Mykhailova, Mathias Soeken:
Testing Quantum Programs using Q# and Microsoft Quantum Development Kit. Q-SET@QCE 2021: 81-88 - 2020
- [j25]Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access 8: 226828-226844 (2020) - [j24]D. Michael Miller, Mathias Soeken:
A Spectral Algorithm for 3-valued Function Equivalence Classification. J. Multiple Valued Log. Soft Comput. 34(3-4): 203-221 (2020) - [j23]Giulia Meuli, Mathias Soeken, Martin Roetteler, Thomas Häner:
Enabling accuracy-aware Quantum compilers using symbolic resource estimation. Proc. ACM Program. Lang. 4(OOPSLA): 130:1-130:26 (2020) - [j22]Winston Haaswijk, Mathias Soeken, Alan Mishchenko, Giovanni De Micheli:
SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 871-884 (2020) - [j21]Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli:
Advanced Functional Decomposition Using Majority and Its Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1621-1634 (2020) - [c135]Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli:
Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). DATE 2020: 133-138 - [c134]Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli:
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. DATE 2020: 568-573 - [c133]Heinz Riener, Alan Mishchenko, Mathias Soeken:
Exact DAG-Aware Rewriting. DATE 2020: 732-737 - [c132]Giulia Meuli, Mathias Soeken, Martin Roetteler, Giovanni De Micheli:
Enumerating Optimal Quantum Circuits using Spectral Classification. ISCAS 2020: 1-5 - [c131]Bruno Schmitt, Mathias Soeken, Giovanni De Micheli:
Symbolic Algorithms for Token Swapping. ISMVL 2020: 28-33 - [c130]Fereshte Mozafari, Mathias Soeken, Heinz Riener, Giovanni De Micheli:
Automatic Uniform Quantum State Preparation Using Decision Diagrams. ISMVL 2020: 170-175 - [c129]Thomas Häner, Samuel Jaques, Michael Naehrig, Martin Roetteler, Mathias Soeken:
Improved Quantum Circuits for Elliptic Curve Discrete Logarithms. PQCrypto 2020: 425-444 - [c128]Mathias Soeken, Martin Roetteler:
Quantum Circuits for Functionally Controlled NOT Gates. QCE 2020: 366-371 - [i20]Thomas Häner, Samuel Jaques, Michael Naehrig, Martin Roetteler, Mathias Soeken:
Improved quantum circuits for elliptic curve discrete logarithms. CoRR abs/2001.09580 (2020) - [i19]Giulia Meuli, Mathias Soeken, Martin Roetteler, Thomas Häner:
Automatic accuracy management of quantum programs via (near-)symbolic resource estimation. CoRR abs/2003.08408 (2020) - [i18]Mathias Soeken:
Determining the Multiplicative Complexity of Boolean Functions using SAT. CoRR abs/2005.01778 (2020) - [i17]Mathias Soeken, Martin Roetteler:
Quantum Circuits for Functionally Controlled NOT Gates. CoRR abs/2005.12310 (2020) - [i16]Thomas Häner, Mathias Soeken:
Lowering the T-depth of Quantum Circuits By Reducing the Multiplicative Depth Of Logic Networks. CoRR abs/2006.03845 (2020) - [i15]Thomas Häner, Samuel Jaques, Michael Naehrig, Martin Roetteler, Mathias Soeken:
Improved Quantum Circuits for Elliptic Curve Discrete Logarithms. IACR Cryptol. ePrint Arch. 2020: 77 (2020) - [i14]Mathias Soeken:
Determining the Multiplicative Complexity of Boolean Functions using SAT. IACR Cryptol. ePrint Arch. 2020: 530 (2020) - [i13]Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli:
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. IACR Cryptol. ePrint Arch. 2020: 706 (2020)
2010 – 2019
- 2019
- [j20]Eleonora Testa, Mathias Soeken, Luca Gaetano Amarù, Giovanni De Micheli:
Logic Synthesis for Established and Emerging Computing. Proc. IEEE 107(1): 165-184 (2019) - [j19]Eleonora Testa, Mathias Soeken, Luca Gaetano Amarù, Winston Haaswijk, Giovanni De Micheli:
Mapping Monotone Boolean Functions into Majority. IEEE Trans. Computers 68(5): 791-797 (2019) - [j18]Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli:
LUT-Based Hierarchical Reversible Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1675-1688 (2019) - [c127]Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli:
Structural rewriting in XOR-majority graphs. ASP-DAC 2019: 663-668 - [c126]Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken:
Scalable Generic Logic Synthesis: One Approach to Rule Them All. DAC 2019: 70 - [c125]Eleonora Testa, Mathias Soeken, Luca G. Amarù, Giovanni De Micheli:
Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications. DAC 2019: 74 - [c124]Giulia Meuli, Mathias Soeken, Martin Roetteler, Nikolaj S. Bjørner, Giovanni De Micheli:
Reversible Pebbling Game for Quantum Memory Management. DATE 2019: 288-291 - [c123]Mathias Soeken, Fereshte Mozafari, Bruno Schmitt, Giovanni De Micheli:
Compiling Permutations for Superconducting QPUs. DATE 2019: 1349-1354 - [c122]Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Scalable Boolean Methods in a Modern Synthesis Flow. DATE 2019: 1643-1648 - [c121]Heinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken:
On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis. DATE 2019: 1649-1654 - [c120]Giulia Meuli, Mathias Soeken, Earl T. Campbell, Martin Roetteler, Giovanni De Micheli:
The Role of Multiplicative Complexity in Compiling Low $T$-count Oracle Circuits. ICCAD 2019: 1-8 - [c119]Zhufei Chu, Winston Haaswijk, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli:
Exact Synthesis of Boolean Functions in Majority-of-Five Forms. ISCAS 2019: 1-5 - [c118]Bruno Schmitt, Mathias Soeken, Giovanni De Micheli, Alan Mishchenko:
Scaling-up ESOP Synthesis for Quantum Compilation. ISMVL 2019: 13-18 - [c117]Debjyoti Bhattacharjee, Mathias Soeken, Srijit Dutta, Anupam Chattopadhyay, Giovanni De Micheli:
Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis. ISMVL 2019: 102-107 - [c116]Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken:
Logic Optimization of Majority-Inverter Graphs. MBMV 2019: 1-4 - [c115]Mathias Soeken, Eleonora Testa, D. Michael Miller:
A Hybrid Method for Spectral Translation Equivalent Boolean Functions. PACRIM 2019: 1-6 - [c114]Mathias Soeken:
Using ZDDs in the mapping of quantum circuits. QPL 2019: 106-118 - [c113]Giulia Meuli, Mathias Soeken, Martin Roetteler, Giovanni De Micheli:
ROS: Resource-constrained Oracle Synthesis for Quantum Computers. QPL 2019: 119-130 - [e1]Michael Kirkedal Thomsen, Mathias Soeken:
Reversible Computation - 11th International Conference, RC 2019, Lausanne, Switzerland, June 24-25, 2019, Proceedings. Lecture Notes in Computer Science 11497, Springer 2019, ISBN 978-3-030-21499-9 [contents] - [i12]Giulia Meuli, Mathias Soeken, Martin Roetteler, Nikolaj S. Bjørner, Giovanni De Micheli:
Reversible Pebbling Game for Quantum Memory Management. CoRR abs/1904.02121 (2019) - [i11]Giulia Meuli, Mathias Soeken, Earl T. Campbell, Martin Roetteler, Giovanni De Micheli:
The Role of Multiplicative Complexity in Compiling Low T-count Oracle Circuits. CoRR abs/1908.01609 (2019) - 2018
- [j17]Oliver Keszöcze, Mathias Soeken, Rolf Drechsler:
The complexity of error metrics. Inf. Process. Lett. 139: 1-7 (2018) - [j16]Mathias Soeken, Eleonora Testa, Alan Mishchenko, Giovanni De Micheli:
Pairs of majority-decomposing functions. Inf. Process. Lett. 139: 35-38 (2018) - [j15]Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler:
Behaviour Driven Development for Hardware Design. IPSJ Trans. Syst. LSI Des. Methodol. 11: 29-45 (2018) - [j14]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler:
Logic Synthesis for RRAM-Based In-Memory Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1422-1435 (2018) - [c112]Giulia Meuli, Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli:
A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis. ASP-DAC 2018: 664-669 - [c111]Zhufei Chu, Mathias Soeken, Yinshui Xia, Giovanni De Micheli:
Functional decomposition using majority. ASP-DAC 2018: 676-681 - [c110]Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic:
Canonical computation without canonical representation. DAC 2018: 52:1-52:6 - [c109]Winston Haaswijk, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli:
SAT based exact synthesis using DAG topology families. DAC 2018: 53:1-53:6 - [c108]Mathias Soeken, Thomas Häner, Martin Roetteler:
Programming quantum computers using design automation. DATE 2018: 137-146 - [c107]Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli:
Practical exact synthesis. DATE 2018: 309-314 - [c106]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Improvements to boolean resynthesis. DATE 2018: 755-760 - [c105]Luca G. Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken:
Majority logic synthesis. ICCAD 2018: 79 - [c104]Winston Haaswijk, Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Mathias Soeken, Giovanni De Micheli:
Integrated ESOP Refactoring for Industrial Designs. ICECS 2018: 369-372 - [c103]Winston Haaswijk, Edo Collins, Benoit Seguin, Mathias Soeken, Frédéric Kaplan, Sabine Süsstrunk, Giovanni De Micheli:
Deep Learning for Logic Optimization Algorithms. ISCAS 2018: 1-4 - [c102]D. Michael Miller, Mathias Soeken:
A Spectral Algorithm for Ternary Function Classification. ISMVL 2018: 198-203 - [c101]Wouter Castryck, Jeroen Demeyer, Alexis De Vos, Oliver Keszöcze, Mathias Soeken:
Translating Between the Roots of the Identity in Quantum Computers. ISMVL 2018: 254-259 - [c100]Heinz Riener, Eleonora Testa, Luca G. Amarù, Mathias Soeken, Giovanni De Micheli:
Size Optimization of MIGs with an Application to QCA and STMG Technologies. NANOARCH 2018: 157-162 - [c99]Thomas Häner, Mathias Soeken, Martin Roetteler, Krysta M. Svore:
Quantum Circuits for Floating-Point Arithmetic. RC 2018: 162-174 - [c98]Giulia Meuli, Mathias Soeken, Giovanni De Micheli:
SAT-based {CNOT, T} Quantum Circuit Synthesis. RC 2018: 175-188 - [i10]Mathias Soeken, Thomas Häner, Martin Roetteler:
Programming Quantum Computers Using Design Automation. CoRR abs/1803.01022 (2018) - [i9]Mathias Soeken, Heinz Riener, Winston Haaswijk, Giovanni De Micheli:
The EPFL Logic Synthesis Libraries. CoRR abs/1805.05121 (2018) - [i8]Thomas Häner, Mathias Soeken, Martin Roetteler, Krysta M. Svore:
Quantum circuits for floating-point arithmetic. CoRR abs/1807.02023 (2018) - 2017
- [j13]Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli:
A PLiM Computer for the Internet of Things. Computer 50(6): 35-40 (2017) - [j12]Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey:
metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. 19(5): 605-621 (2017) - [j11]Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Exact Synthesis of Majority-Inverter Graphs and Its Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(11): 1842-1855 (2017) - [c97]Winston Haaswijk, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A novel basis for logic rewriting. ASP-DAC 2017: 151-156 - [c96]Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Multi-level logic benchmarks: An exactness study. ASP-DAC 2017: 157-162 - [c95]Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli:
Hierarchical Reversible Logic Synthesis Using LUTs. DAC 2017: 78:1-78:6 - [c94]Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli:
Design automation and design space exploration for quantum computers. DATE 2017: 470-475 - [c93]Mathias Soeken, Giovanni De Micheli, Alan Mishchenko:
Busy man's synthesis: Combinational delay optimization with SAT. DATE 2017: 830-835 - [c92]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler:
Endurance management for resistive Logic-In-Memory computing architectures. DATE 2017: 1092-1097 - [c91]Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins:
Wave pipelining for majority-based beyond-CMOS technologies. DATE 2017: 1306-1311 - [c90]Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler:
An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization. GECCO 2017: 1232-1239 - [c89]Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI 2017: 131-136 - [c88]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Enabling exact delay synthesis. ICCAD 2017: 352-359 - [c87]Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
RM3 based logic synthesis (Special session paper). ISCAS 2017: 1-4 - [c86]Winston Haaswijk, Eleonora Testa, Mathias Soeken, Giovanni De Micheli:
Classifying Functions with Exact Synthesis. ISMVL 2017: 272-277 - [c85]Eleonora Testa, Odysseas Zografos, Mathias Soeken, Adrien Vaysset, Mauricio Manfrini, Rudy Lauwereins, Giovanni De Micheli:
Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies. ISVLSI 2017: 164-169 - [i7]Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli:
Logic Synthesis for Quantum Computing. CoRR abs/1706.02721 (2017) - 2016
- [j10]Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler:
Verifying the structure and behavior in UML/OCL models using satisfiability solvers. IET Cyper-Phys. Syst.: Theory & Appl. 1(1): 49-59 (2016) - [j9]Robert Wille, Eleonora Schönborn, Mathias Soeken, Rolf Drechsler:
SyReC: A hardware description language for the specification and synthesis of reversible circuits. Integr. 53: 39-53 (2016) - [j8]Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler:
Embedding of Large Boolean Functions for Reversible Logic. ACM J. Emerg. Technol. Comput. Syst. 12(4): 41:1-41:26 (2016) - [j7]Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler:
Ancilla-free synthesis of large reversible functions using binary decision diagrams. J. Symb. Comput. 73: 1-26 (2016) - [j6]Nabila Abdessaied, Matthew Amy, Rolf Drechsler, Mathias Soeken:
Complexity of reversible circuits and their quantum implementations. Theor. Comput. Sci. 618: 85-106 (2016) - [c84]Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler:
BDD minimization for approximate computing. ASP-DAC 2016: 474-479 - [c83]Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli:
An MIG-based compiler for programmable logic-in-memory architectures. DAC 2016: 117:1-117:6 - [c82]Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler:
Precise error determination of approximated components in sequential circuits with model checking. DAC 2016: 129:1-129:6 - [c81]Mathias Soeken, Anupam Chattopadhyay:
Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis. DAC 2016: 149:1-149:6 - [c80]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler:
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. DATE 2016: 948-953 - [c79]Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Optimizing Majority-Inverter Graphs with functional hashing. DATE 2016: 1030-1035 - [c78]Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler:
Formal verification of integer multipliers by combining Gröbner basis with logic reduction. DATE 2016: 1048-1053 - [c77]Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler:
Multi-objective BDD optimization for RRAM based circuit design. DDECS 2016: 46-51 - [c76]Amr A. R. Sayed-Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler:
Equivalence checking using Gröbner bases. FMCAD 2016: 169-176 - [c75]Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko:
Fast hierarchical NPN classification. FPL 2016: 1-4 - [c74]Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler:
Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. GECCO (Companion) 2016: 79-80 - [c73]Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer:
SAT-Based Combinational and Sequential Dependency Computation. Haifa Verification Conference 2016: 1-17 - [c72]Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne:
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD 2016: 4 - [c71]Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler:
Approximation-aware rewriting of AIGs for error tolerant applications. ICCAD 2016: 83 - [c70]Sandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken:
Multilevel design understanding: from specification to logic (invited paper). ICCAD 2016: 133 - [c69]Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller:
An extension of transformation-based reversible and quantum circuit synthesis. ISCAS 2016: 2290-2293 - [c68]Anupam Chattopadhyay, Luca Gaetano Amarù, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Notes on Majority Boolean Algebra. ISMVL 2016: 50-55 - [c67]Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler:
Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits. ISMVL 2016: 150-155 - [c66]Johanna Sepúlveda, Daniel Florez, Mathias Soeken, Jean-Philippe Diguet, Guy Gogniat:
Dynamic NoC buffer allocation for MPSoC timing side channel attack protection. LASCAS 2016: 91-94 - [c65]Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler:
Symbolic Error Metric Determination for Approximate Computing. MBMV 2016: 75-76 - [c64]Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Inversion optimization in Majority-Inverter Graphs. NANOARCH 2016: 15-20 - [c63]Mathias Soeken, Nabila Abdessaied, Giovanni De Micheli:
Enumeration of Reversible Functions and Its Application to Circuit Complexity. RC 2016: 255-270 - [c62]Mathias Soeken, Gerhard W. Dueck, D. Michael Miller:
A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis. RC 2016: 307-321 - [c61]Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli:
Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT 2016: 212-227 - [i6]Mathias Soeken, Martin Rötteler, Nathan Wiebe, Giovanni De Micheli:
Design Automation and Design Space Exploration for Quantum Computers. CoRR abs/1612.00631 (2016) - 2015
- [b2]Mathias Soeken, Rolf Drechsler:
Formal Specification Level - Concepts, Methods, and Algorithms. Springer 2015, ISBN 978-3-319-08698-9, pp. I-VIII, 1-138 - [j5]Esther Guerra, Mathias Soeken:
Specification-driven model transformation testing. Softw. Syst. Model. 14(2): 623-644 (2015) - [c60]Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler:
Requirement Phrasing Assistance Using Automatic Quality Assessment. DDECS 2015: 183-188 - [c59]Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton:
Simulation Graphs for Reverse Engineering. FMCAD 2015: 152-159 - [c58]Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler:
Multi-Objective BDD Optimization with Evolutionary Algorithms. GECCO 2015: 751-758 - [c57]Mathias Soeken, Anupam Chattopadhyay:
Fredkin-Enabled Transformation-Based Reversible Logic Synthesis. ISMVL 2015: 60-65 - [c56]Md. Mazder Rahman, Mathias Soeken, Gerhard W. Dueck:
Dynamic Template Matching with Mixed-Polarity Toffoli Gates. ISMVL 2015: 72-77 - [c55]Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler:
Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. MoDeVVa@MoDELS 2015: 44-47 - [c54]Michael Kirkedal Thomsen, Robin Kaarsgaard, Mathias Soeken:
Ricercar: A Language for Describing and Rewriting Reversible Circuits with Ancillae and Its Permutation Semantics. RC 2015: 200-215 - [c53]Nabila Abdessaied, Mathias Soeken, Rolf Drechsler:
Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition. RC 2015: 219-232 - [c52]Mathias Soeken, Julia Seiter, Rolf Drechsler:
Coverage of OCL Operation Specifications and Invariants. TAP@STAF 2015: 191-207 - [c51]Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler:
Reversible circuit rewriting with simulated annealing. VLSI-SoC 2015: 286-291 - [i5]Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller:
Self-Inverse Functions and Palindromic Circuits. CoRR abs/1502.05825 (2015) - 2014
- [j4]Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler:
Trading off circuit lines and gate costs in the synthesis of reversible logic. Integr. 47(2): 284-294 (2014) - [j3]Nabila Abdessaied, Mathias Soeken, Michael Kirkedal Thomsen, Rolf Drechsler:
Upper bounds for reversible circuits based on Young subgroups. Inf. Process. Lett. 114(6): 282-286 (2014) - [c50]Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler:
MetaSMT: a unified interface to SMT-LIB2. FDL 2014: 1-6 - [c49]Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris, Rolf Drechsler:
Automating the translation of assertions using natural language processing techniques. FDL 2014: 1-8 - [c48]Rolf Drechsler, Mathias Soeken, Robert Wille:
Automated and quality-driven requirements engineering. ICCAD 2014: 586-590 - [c47]Stefan A. Wiesner, Christian Gorldt, Mathias Soeken, Klaus-Dieter Thoben, Rolf Drechsler:
Requirements Engineering for Cyber-Physical Systems - Challenges in the Context of "Industrie 4.0". APMS (1) 2014: 281-288 - [c46]Mathias Soeken, Max Nitze, Rolf Drechsler:
Formale Methoden für Alle. MBMV 2014: 213-216 - [c45]Nabila Abdessaied, Mathias Soeken, Rolf Drechsler:
Quantum Circuit Optimization by Hadamard Gate Reduction. RC 2014: 149-162 - [c44]D. Michael Miller, Mathias Soeken, Rolf Drechsler:
Mapping NCV Circuits to Optimized Clifford+T Circuits. RC 2014: 163-175 - [c43]Rolf Drechsler, Hoang Minh Le, Mathias Soeken:
Self-Verification as the Key Technology for Next Generation Electronic Systems. SBCCI 2014: 15:1-15:4 - [c42]Fritjof Bornebusch, Glaucia Cancino, Melanie Diepenbeck, Rolf Drechsler, Smith Djomkam, Alvine Nzeungang Fanseu, Maryam Jalali, Marc Michael, Jamal Mohsen, Max Nitze, Christina Plump, Mathias Soeken, Hubert Fred Tchambo, Toni, Henning Ziegler:
iTac: Aspect Based Sentiment Analysis using Sentiment Trees and Dictionaries. SemEval@COLING 2014: 351-355 - [c41]Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler:
Behaviour Driven Development for Tests and Verification. TAP@STAF 2014: 61-77 - [i4]Mathias Soeken, Nabila Abdessaied, Rolf Drechsler:
A framework for reversible circuit complexity. CoRR abs/1407.5878 (2014) - [i3]Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler:
Embedding of Large Boolean Functions for Reversible Logic. CoRR abs/1408.3586 (2014) - [i2]Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler:
Ancilla-free synthesis of large reversible functions using binary decision diagrams. CoRR abs/1408.3955 (2014) - 2013
- [b1]Mathias Soeken:
Formal specification level: concepts, methods, and algorithms. University of Bremen, 2013, pp. 1-128 - [j2]Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler:
Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits. J. Multiple Valued Log. Soft Comput. 21(5-6): 627-640 (2013) - [c40]Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler:
Improving the mapping of reversible circuits to quantum circuits using multiple target lines. ASP-DAC 2013: 145-150 - [c39]Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler:
Determining relevant model elements for the verification of UML/OCL specifications. DATE 2013: 1189-1192 - [c38]Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler:
Towards a generic verification methodology for system models. DATE 2013: 1193-1196 - [c37]Rolf Drechsler, Mathias Soeken:
Hardware-Software Co-Visualization: Developing systems in the holodeck. DDECS 2013: 1-4 - [c36]Rolf Drechsler, Mathias Soeken, Robert Wille:
Text statt C++: Automatisierung des Systementwurfs mit Hilfe natürlicher Sprachverarbeitung. GI-Jahrestagung 2013: 151 - [c35]Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler:
Towards automatic scenario generation from coverage information. AST 2013: 82-88 - [c34]Mathias Soeken, Rolf Drechsler:
Grammar-based program generation based on model finding. IDT 2013: 1-5 - [c33]Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler:
Debugging of Reversible Circuits Using pDDs. ISMVL 2013: 316-321 - [c32]Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler:
Exact Template Matching Using Boolean Satisfiability. ISMVL 2013: 328-333 - [c31]Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler:
Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen. MBMV 2013: 99-103 - [c30]Mathias Soeken, Michael Kirkedal Thomsen:
White Dots do Matter: Rewriting Reversible Logic Circuits. RC 2013: 196-208 - [c29]Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler:
Reducing the Depth of Quantum Circuits Using Additional Circuit Lines. RC 2013: 221-233 - [p1]Mathias Soeken:
Formale Spezifikationsebene. Ausgezeichnete Informatikdissertationen 2013: 241-250 - [i1]Mathias Soeken, D. Michael Miller, Rolf Drechsler:
On quantum circuits employing roots of the Pauli matrices. CoRR abs/1308.2493 (2013) - 2012
- [j1]Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler:
RevKit: A Toolkit for Reversible Circuit Design. J. Multiple Valued Log. Soft Comput. 18(1): 55-65 (2012) - [c28]Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler:
Synthesis of reversible circuits with minimal lines for large functions. ASP-DAC 2012: 85-92 - [c27]Robert Wille, Mathias Soeken, Rolf Drechsler:
Debugging of inconsistent UML/OCL models. DATE 2012: 1078-1083 - [c26]Mathias Soeken, Robert Wille, Rolf Drechsler:
Eliminating invariants in UML/OCL models. DATE 2012: 1142-1145 - [c25]Rolf Drechsler, Mathias Soeken, Robert Wille:
Formal Specification Level. FDL (Selected Papers) 2012: 37-52 - [c24]Rolf Drechsler, Mathias Soeken, Robert Wille:
Formal Specification Level: Towards verification-driven design based on natural language processing. FDL 2012: 53-58 - [c23]Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang Minh Le, Julia Seiter, Mathias Soeken, Robert Wille:
Completeness-Driven Development. ICGT 2012: 38-50 - [c22]Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler:
Behavior Driven Development for circuit design and verification. HLDVT 2012: 9-16 - [c21]Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler:
Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines. ISMVL 2012: 69-74 - [c20]Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler:
Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits. ISMVL 2012: 173-178 - [c19]Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler:
A Synthesis Flow for Sequential Reversible Circuits. ISMVL 2012: 299-304 - [c18]Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler:
Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. ISVLSI 2012: 213-218 - [c17]Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler:
Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams. RC 2012: 183-196 - [c16]Mathias Soeken, Robert Wille, Shin-ichi Minato, Rolf Drechsler:
Using πDDs in the Design of Reversible Circuits. RC 2012: 197-203 - [c15]Mathias Soeken, Robert Wille, Rolf Drechsler:
Assisted Behavior Driven Development Using Natural Language Processing. TOOLS (50) 2012: 269-287 - 2011
- [c14]Mathias Soeken, Robert Wille, Rolf Drechsler:
Verifying dynamic aspects of UML models. DATE 2011: 1077-1082 - [c13]Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler:
Automatic property generation for the formal verification of bus bridges. DDECS 2011: 417-422 - [c12]Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler:
Designing a RISC CPU in Reversible Logic. ISMVL 2011: 170-175 - [c11]Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler:
Towards Automatic Property Generation for the Formal Verification of Bus Bridges. MBMV 2011: 183-192 - [c10]Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler:
Designing a RISC CPU in Reversible Logic. MBMV 2011: 249-258 - [c9]Mathias Soeken, Robert Wille, Rolf Drechsler:
Towards automatic determination of problem bounds for object instantiation in static model verification. MoDeVVa@MoDELS 2011: 2:1-2:4 - [c8]Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler:
RevKit: An Open Source Toolkit for the Design of Reversible Circuits. RC 2011: 64-76 - [c7]Mathias Soeken, Robert Wille, Rolf Drechsler:
Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models. TAP@TOOLS 2011: 152-170 - 2010
- [c6]Robert Wille, Mathias Soeken, Rolf Drechsler:
Reducing the number of lines in reversible circuits. DAC 2010: 647-652 - [c5]Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler:
Verifying UML/OCL models using Boolean satisfiability. DATE 2010: 1341-1344 - [c4]Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler:
Window optimization of reversible and quantum circuits. DDECS 2010: 341-345 - [c3]Mathias Soeken, Robert Wille, Rolf Drechsler:
Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition. IDT 2010: 143-148 - [c2]Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler:
Verifying UML/OCL Models Using Boolean Satisfiability. MBMV 2010: 57-66
2000 – 2009
- 2008
- [c1]Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler:
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. ISVLSI 2008: 411-416
Coauthor Index
Luca G. Amarù
aka: Luca Gaetano Amarù
aka: Luca Gaetano Amarù
[j17] [j15] [j14] [j13] [j12] [c92] [c90] [j10] [j9] [j8] [j7] [j6] [c84] [c83] [c82] [c80] [c78] [c77] [c76] [c74] [c71] [c67] [c65] [b2] [c60] [c59] [c58] [c55] [c53] [c52] [c51] [j4] [j3] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [i4] [i3] [i2] [j2] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c29] [i1] [j1] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
[j28] [j27] [j26] [j25] [j22] [j21] [c135] [c134] [c132] [c131] [c130] [i13] [j20] [j19] [j18] [c127] [c126] [c125] [c124] [c123] [c122] [c121] [c120] [c119] [c118] [c117] [c116] [c113] [i12] [i11] [j16] [c112] [c111] [c109] [c107] [c106] [c105] [c104] [c103] [c100] [c98] [i9] [j13] [j11] [c97] [c96] [c95] [c94] [c93] [c92] [c91] [c89] [c88] [c87] [c86] [c85] [i7] [c83] [c79] [c75] [c73] [c72] [c68] [c64] [c63] [c61] [i6]
Martin Rötteler
aka: Martin Roetteler
aka: Martin Roetteler
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