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2020 – today
- 2023
[j1]Amit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan
, Rahul Singhal:
Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O. IEEE Des. Test 40(4): 17-24 (2023)- 2022
- [c10]Likith Kumar Manchukonda, Karthikeyan Natarajan, Manish Arora:
Power Aware Test. ETS 2022: 1 - [c9]Khader S. Abdel-Hafez, Michael Dsouza, Likith Kumar Manchukonda, Elddie Tsai, Karthikeyan Natarajan, Ting-Pu Tai, Wenhao Hsueh, Smith Lai:
Comprehensive Power-Aware ATPG Methodology for Complex Low-Power Designs. ITC 2022: 334-339 - [c8]Amit Pandey, Brendan Tully, Karthikeyan Natarajan:
High Speed IO Access for Test forms the foundation for Silicon Lifecycle Management. ITC 2022: 656-660 - [c7]Amit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal:
Novel Technique for Manufacturing & In-system Testing of Large Scale SoC using Functional Protocol Based High-Speed I/O. VTS 2022: 1-7
2010 – 2019
- 2019
- [c6]Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu:
High Performance Graph Convolutional Networks with Applications in Testability Analysis. DAC 2019: 18 - 2018
- [c5]Karthikeyan Natarajan, Nitin Chandrachoodan:
Lossless Parallel Implementation of a Turbo Decoder on GPU. HiPC 2018: 133-142 - 2016
- [c4]Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha:
Dynamic docking architecture for concurrent testing and peak power reduction. VTS 2016: 1-6 - [c3]Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani:
A programmable method for low-power scan shift in SoC integrated circuits. VTS 2016: 1-6 - 2015
- [c2]Karthikeyan Natarajan, Nitin Chandrachoodan:
Non-uniform DFT implementation for channel simulations in GPU. NCC 2015: 1-6 - 2011
- [c1]Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu:
Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. VTS 2011: 219-224
Coauthor Index
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