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ORCIDYuzo Takamatsu
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2000 – 2009
- 2009
[j24]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Addressing Defect Coverage through Generating Test Vectors for Transistor Defects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3128-3135 (2009)- [j23]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu:
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. Inf. Media Technol. 4(4): 727-739 (2009) - [j22]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. IPSJ Trans. Syst. LSI Des. Methodol. 2: 250-262 (2009) - [c42]Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
New Class of Tests for Open Faults with Considering Adjacent Lines. Asian Test Symposium 2009: 301-306 - [c41]Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu:
Diagnostic test generation for transition faults using a stuck-at ATPG tool. ITC 2009: 1-9 - [c40]Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
A Novel Approach for Improving the Quality of Open Fault Diagnosis. VLSI Design 2009: 85-90 - [c39]Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu:
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. VLSI Design 2009: 91-96 - 2008
- [j21]Koji Yamazaki, Yuzo Takamatsu:
A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information. IEICE Trans. Inf. Syst. 91-D(3): 661-666 (2008) - [j20]Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki:
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information. IEICE Trans. Inf. Syst. 91-D(3): 675-682 (2008) - [j19]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. IEICE Trans. Inf. Syst. 91-D(3): 690-699 (2008) - [j18]Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato:
Post-BIST Fault Diagnosis for Multiple Faults. IEICE Trans. Inf. Syst. 91-D(3): 771-775 (2008) - [j17]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3506-3513 (2008) - [c38]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults. ATS 2008: 97-102 - 2007
- [c37]Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines. ATS 2007: 39-44 - [c36]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator. ATS 2007: 271-274 - [c35]Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu:
Timing-Aware Diagnosis for Small Delay Defects. DFT 2007: 223-234 - [c34]Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. DFT 2007: 243-251 - [c33]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu:
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. VLSI Design 2007: 781-786 - 2006
- [j16]Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu:
On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Trans. Inf. Syst. 89-D(11): 2748-2755 (2006) - [c32]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. ASP-DAC 2006: 659-664 - [c31]Koji Yamazaki, Yuzo Takamatsu:
Fanout-based fault diagnosis for open faults on pass/fail information. ATS 2006: 349-353 - [c30]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu:
Diagnosis of Transistor Shorts in Logic Test Environment. ATS 2006: 354-359 - [c29]Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato:
Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT 2006: 401-109 - 2005
- [j15]Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu:
Test cost reduction for logic circuits: Reduction of test data volume and test application time. Syst. Comput. Jpn. 36(6): 69-83 (2005) - [j14]Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu:
A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 252-263 (2005) - [c28]T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu:
On the fault diagnosis in the presence of unknown fault models using pass/fail information. ISCAS (3) 2005: 2987-2990 - 2004
- [j13]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu:
Generation of Test Sequences with Low Power Dissipation for Sequential Circuits. IEICE Trans. Inf. Syst. 87-D(3): 530-536 (2004) - [c27]Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu:
Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. Asian Test Symposium 2004: 46-49 - [c26]Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu:
Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. Asian Test Symposium 2004: 216-221 - [c25]Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu:
Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. Asian Test Symposium 2004: 222-227 - 2003
- [c24]Hiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu:
BIST Based Fault Diagnosis Using Ambiguous Test Set. DFT 2003: 89-96 - [c23]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz:
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ICCD 2003: 397- - 2002
- [j12]Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu:
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3): 362-368 (2002) - [c22]Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu:
Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. Asian Test Symposium 2002: 242-247 - [c21]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu:
A Method to Reduce Power Dissipation during Test for Sequential Circuits. Asian Test Symposium 2002: 326-331 - [c20]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu:
Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. DELTA 2002: 431-433 - [c19]Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu:
An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. PRDC 2002: 275-282 - 2001
- [c18]Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu:
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. Asian Test Symposium 2001: 63- - [c17]Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu:
Test Generation for Double Stuck-at Faults. Asian Test Symposium 2001: 71-75 - [c16]Keith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu:
On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits. ITC 2001: 568-577 - 2000
- [j11]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electron. Test. 16(5): 443-451 (2000) - [j10]Tetsuro Minamiyama, Yuzo Takamatsu:
Identification of redundant faults in combinational circuits. Syst. Comput. Jpn. 31(6): 65-73 (2000) - [j9]Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita:
Static test compaction for IDDQ testing of bridging faults in sequential circuits. Syst. Comput. Jpn. 31(11): 41-50 (2000) - [c15]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Fault models and test generation for IDDQ testing: embedded tutorial. ASP-DAC 2000: 509-514 - [c14]Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita:
Test sequence compaction for sequential circuits with reset states. Asian Test Symposium 2000: 165-170 - [c13]Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu:
General BIST-Amenable Method of Test Generation for Iterative Logic Arrays. VTS 2000: 171-178
1990 – 1999
- 1999
- [c12]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 141-146 - [c11]Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Nobuhiro Yanagida:
Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators. Asian Test Symposium 1999: 341-346 - [c10]Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu:
A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations. VTS 1999: 64-69 - 1998
- [c9]Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu:
Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation. Asian Test Symposium 1998: 108-112 - [c8]Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu:
Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths. Asian Test Symposium 1998: 237- - 1997
- [j8]Hiroshi Takahashi, Takashi Watanabe, Toshiyuki Matsunaga, Yuzo Takamatsu:
Tests for small gate delay faults in combinational circuits and a test generation method. Syst. Comput. Jpn. 28(6): 68-76 (1997) - [c7]Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu:
Design of C-Testable Multipliers Based on the Modified Booth Algorithm. Asian Test Symposium 1997: 42-47 - [c6]Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga:
A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. Asian Test Symposium 1997: 320-325 - 1996
- [c5]Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu:
Multiple Fault Diagnosis in Sequential Circuits Using Sensitizing Sequence Pairs. FTCS 1996: 86-95 - 1995
- [j7]Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu:
Multiple Fault Diagnosis by Sensitizing Input Pairs. IEEE Des. Test Comput. 12(3): 44-52 (1995) - [j6]Xiangqiu Yu, Hiroshi Takahashi, Yuzo Takamatsu:
A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects. IEICE Trans. Inf. Syst. 78-D(7): 822-829 (1995) - [j5]Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu:
Multiple fault diagnosis in combinational circuits using sensitizing input-pairs. Syst. Comput. Jpn. 26(3): 17-29 (1995) - [j4]Yuzo Takamatsu, Isao Higashi, Tsuyoshi Kodama:
Test generation for sequential circuits using parallel fault simulation with random inputs. Syst. Comput. Jpn. 26(10): 24-34 (1995) - [c4]Hiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu:
Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing. Asian Test Symposium 1995: 58-64 - [c3]Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu:
Generation of tenacious tests for small gate delay faults in combinational circuits. Asian Test Symposium 1995: 332-338 - 1990
- [j3]Yuzo Takamatsu, Kozo Kinoshita:
Extended selection of switching target faults in CONT algorithm for test generation. J. Electron. Test. 1(3): 183-189 (1990) - [c2]Masakatu Morii, Yuzo Takamatsu:
Exponetiation in Finite Fields Using Dual Basis Multiplier. AAECC 1990: 354-366
1980 – 1989
- 1989
- [j2]Yuzo Takamatsu, Kozo Kinoshita:
CONT: a concurrent test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(9): 966-972 (1989) - 1988
- [j1]Hideo Fujiwara, Yuzo Takamatsu, Takashi Nanya, Teruhiko Yamada, Hideo Tamamoto, Kiyoshi Furuya:
Test research in Japan. IEEE Des. Test 5(5): 60-79 (1988) - 1983
- [c1]Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara:
Test generation for scan design circuits with tri-state modules and bidirectional terminals. DAC 1983: 71-78
Coauthor Index
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