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ORCIDHironori Yamauchi
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2010 – 2019
- 2019
[c17]Suhail Hamdan, Yohei Fukumizu, Tomonori Izumi, Hironori Yamauchi:
Improved face image super-resolution with restricted patch-searching area. ICCSP 2019: 184-190- 2012
- [c16]Kenji Hashiodani, S. Takada, Yohei Fukumizu, Hironori Yamauchi, Yoshimasa Kurumi, Tohru Tani:
Robustly separating sound components in human body based on 2-ch ICA and EM algorithm with dirichlet distribution. BHI 2012: 56-59 - 2010
- [c15]Abdullah K. Khan, Tatsuya Onoue, Kenji Hashiodani, Yohei Fukumizu, Hironori Yamauchi:
Signal and noise separation in medical diagnostic system based on independent component analysis. APCCAS 2010: 812-815
2000 – 2009
- 2009
- [c14]Yohei Fukumizu, Tomoaki Takano, Yasuyuki Oshima, Toshihiko Terada, Hironori Yamauchi:
A Gabor Pseudo Fisherface Based Face Recognition Algorithm for LSI Implementation. IIH-MSP 2009: 1342-1345 - 2008
- [j4]Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Terai:
Hybrid Architecture of Genetic Algorithm and Simulated Annealing. Eng. Lett. 16(3): 339-345 (2008) - [c13]Toshiyuki Kato, Takaaki Miyauchi, Yoshizo Osumi, Hironori Yamauchi, Hideto Nishikado, Takaaki Miyake, Shiro Kobayashi:
A CDFG generating method from C program for LSI design. APCCAS 2008: 936-939 - 2006
- [c12]Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi:
Configurable multi-processor architecture and its processor element design. ASP-DAC 2006: 124-125 - [c11]Akira Utsumi, Hirotake Yamazoe, Shinji Abe, Daisuke Kanbara, Hironori Yamauchi:
Human Behavior Recognition for Daily Task Assistance using Sparse Range Data Observations. ICARCV 2006: 1-6 - 2005
- [c10]Sadi Vural, Hiromi Tomii, Hironori Yamauchi:
Video watermarking for digital cinema contents. EUSIPCO 2005: 1-6 - [c9]Sadi Vural, Hiromi Tomii, Hironori Yamauchi:
Traceable robust watermarking for digital cinema system. ISSPA 2005: 98-102 - [c8]Sadi Vural, Hiromi Tomii, Hironori Yamauchi:
DWT Based Robust Watermarking Embed Using CRC-32 Techniques. WEC (5) 2005: 106-109 - 2004
- [c7]Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi:
VLSI processor architecture for real-time GA processing and PE-VLSI design. ISCAS (3) 2004: 625-628 - 2002
- [j3]Hideto Nishikado, Hiroyuki Murata, Motonori Yamaji, Hironori Yamauchi:
Blurred Image Restoration by Using Real-Coded Genetic Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(9): 2118-2126 (2002) - [c6]Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi:
Scalable GA processor architecture and its implementation of processor-element. ICASSP 2002: 3148-3151
1990 – 1999
- 1997
- [j2]Keshab K. Parhi
, Takao Nishitani, Hironori Yamauchi:
Guest Editors' Introduction. J. VLSI Signal Process. 16(1): 5-7 (1997) - 1992
- [j1]Hironori Yamauchi, Yutaka Tashiro, Toshihiro Minami, Yutaka Suzuki:
Architecture and implementation of a highly parallel single-chip video DSP. IEEE Trans. Circuits Syst. Video Technol. 2(2): 207-220 (1992) - 1991
- [c5]Hiroshi Miyanaga, Hironori Yamauchi, Kazuhiro Matsuda:
A real-time 256×256 point two-dimensional FFT single-chip processor. ICASSP 1991: 1193-1196 - [c4]Hironori Yamauchi, Yutaka Tashiro, Toshihiro Minami, Yutaka Suzuki:
A highly-parallel single-chip DSP architecture for video signal processing. ICASSP 1991: 1197-1200 - [c3]Yutaka Tashiro, Hironori Yamauchi, Toshihiro Minami, Tetsuo Tajiri, Yutaka Suzuki:
An Organized Firmware Verification Environment for the Programmable Image DSP. ITC 1991: 1034-1041
1980 – 1989
- 1986
- [c2]Takao Kaneko, Hironori Yamauchi, Atsushi Iwata:
A 50ns floating-point signal processor VLSI. ICASSP 1986: 401-404 - 1985
- [c1]Hironori Yamauchi, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata, Sadayasu Ono:
An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM. ICASSP 1985: 204-207
Coauthor Index
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