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ORCIDAshok Jagannathan
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2010 – 2019
- 2017
[c9]Swagath Venkataramani, Ashish Ranjan
, Subarno Banerjee, Dipankar Das, Sasikanth Avancha, Ashok Jagannathan, Ajaya Durg, Dheemanth Nagaraj, Bharat Kaul, Pradeep Dubey, Anand Raghunathan:
ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks. ISCA 2017: 13-26- 2014
- [c8]Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan:
Array scalarization in high level synthesis. ASP-DAC 2014: 622-627
2000 – 2009
- 2007
- [j3]Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski:
Accelerating Sequential Applications on CMPs Using Core Spilling. IEEE Trans. Parallel Distributed Syst. 18(8): 1094-1107 (2007) - 2006
- [c7]Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang:
An automated design flow for 3D microarchitecture evaluation. ASP-DAC 2006: 384-389 - 2005
- [c6]Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong:
Microarchitecture evaluation with floorplanning and interconnect pipelining. ASP-DAC 2005: 8-15 - [c5]Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang:
Instruction set extension with shadow registers for configurable processors. FPGA 2005: 99-106 - [c4]Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir:
Understanding the energy efficiency of SMT and CMP with multiclustering. ISLPED 2005: 48-53 - 2003
- [c3]Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis:
Microarchitecture evaluation with physical planning. DAC 2003: 32-35 - 2002
- [j2]Ashok Jagannathan, Sung-Woo Hur, John Lillis:
A fast algorithm for context-aware buffer insertion. ACM Trans. Design Autom. Electr. Syst. 7(1): 173-188 (2002) - 2000
- [j1]Sung-Woo Hur, Ashok Jagannathan, John Lillis:
Timing-driven maze routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 234-241 (2000) - [c2]Ashok Jagannathan, Sung-Woo Hur, John Lillis:
A fast algorithm for context-aware buffer insertion. DAC 2000: 368-373
1990 – 1999
- 1999
- [c1]Sung-Woo Hur, Ashok Jagannathan, John Lillis:
Timing driven maze routing. ISPD 1999: 208-213
Coauthor Index
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