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2020 – today
- 2021
[j5]Chih-Wei Tsai
, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng:
A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications. IEEE Trans. Very Large Scale Integr. Syst. 29(10): 1720-1729 (2021)
2010 – 2019
- 2019
- [c8]Jieqiong Du, Chien-Heng Wong, Yo-Hao Tu, Wei-Han Cho, Yilei Li, Yuan Du, Po-Tsang Huang, Sheau Jiung Lee, Mau-Chung Frank Chang:
A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET. NOCS 2019: 16:1-16:8 - 2018
- [j4]Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Chi-Yang Chang:
Low supply voltage and multiphase all-digital crystal-less clock generator. IET Circuits Devices Syst. 12(6): 720-725 (2018) - [j3]Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, Jen-Chieh Liu:
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2097-2108 (2018) - [c7]Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng:
A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application. ISCAS 2018: 1-4 - 2017
- [c6]Yo-Hao Tu, Kai-Wen Yao, Minghao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, Jia-Shiang Fu:
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering. VLSI-DAT 2017: 1-4 - 2016
- [j2]Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu:
A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. IEICE Electron. Express 13(2): 20150950 (2016) - [j1]Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng:
Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture. IEICE Trans. Electron. 99-C(6): 655-658 (2016) - [c5]Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang:
A chaotically injected timing technique for ring-based oscillators. DDECS 2016: 31-34 - 2015
- [c4]Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, Hong-Yi Huang:
A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. DDECS 2015: 79-82 - 2014
- [c3]Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang:
A low supply voltage synchronous mirror delay with quadrature phase output. DDECS 2014: 163-166 - 2013
- [c2]Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang:
A low jitter delay-locked-loop applied for DDR4. DDECS 2013: 98-101 - 2010
- [c1]Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng:
A 3 GHz DLL-based clock generator with stuck locking protection. ICECS 2010: 106-109
Coauthor Index
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