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2020 – today
- 2024
[j37]Pudi Dhilleswararao
, Shivam Malviya, Srinivas Boppu, Yu Yang, Ahmed Hemani, Linga Reddy Cenkeramaddi:
Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework. IEEE Access 12: 124081-124094 (2024)- [j36]Pudi Dhilleswararao, Yu Yang, Dimitrios Stathis, Sunil Kumar Prajapati, Srinivas Boppu, Ahmed Hemani, Linga Reddy Cenkeramaddi:
Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study. IEEE Access 12: 155885-155903 (2024) - [j35]Pudi Dhilleswararao, Utsav Tiwari, Srinivas Boppu, Yu Yang, Ahmed Hemani:
Automating functional unit and register binding for synchoros CGRA platform. Des. Autom. Embed. Syst. 28(2): 155-186 (2024) - [j34]Jiawei Xu, Yi Zheng, Feng Li, Dimitrios Stathis, Ruisi Shen, Haoming Chu, Anders Lansner, Lirong Zheng, Zhuo Zou, Ahmed Hemani:
Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning. IEEE Trans. Circuits Syst. II Express Briefs 71(2): 627-631 (2024) - [j33]Haider Abbas, Muhammad Shahzad, Maliha Safdar, Ahmed Hemani:
DUDE: Decryption, Unpacking, Deobfuscation, and Endian Conversion Framework for Embedded Devices Firmware. IEEE Trans. Dependable Secur. Comput. 21(4): 2917-2929 (2024) - [c123]Deyu Wang, Yuning Wang, Yu Yang, Dimitrios Stathis, Ahmed Hemani, Anders Lansner, Jiawei Xu, Li-Rong Zheng, Zhuo Zou:
FPGA-Based HPC for Associative Memory System. ASPDAC 2024: 52-57 - [i7]Yu Yang, Jordi Altayó González, Ahmed Hemani:
CIS: Composable Instruction Set for Streaming Applications: Design, Modeling, and Scheduling. CoRR abs/2407.00207 (2024) - 2023
- [j32]Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani:
Clock tree generation by abutment in synchoros VLSI design. Microprocess. Microsystems 102: 104913 (2023) - [j31]Deyu Wang, Jiawei Xu, Feng Li, Lianhao Zhang, Chengwei Cao, Dimitrios Stathis, Anders Lansner, Ahmed Hemani, Lirong Zheng, Zhuo Zou:
A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning. IEEE Trans. Biomed. Circuits Syst. 17(5): 1153-1165 (2023) - [c122]Pudi Dhilleswararao, Rajeev Ryansh, Vamsi Goudu, Srinivas Boppu, Ahmed Hemani:
Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures. DSD 2023: 16-23 - [c121]Pudi Dhilleswararao, Rajeev Ryansh, Srinivas Boppu, Yu Yang, Ahmed Hemani:
Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures. HEART 2023: 86-92 - [c120]Seyed Ahmad Mirsalari, Saba Yousefzadeh, Giuseppe Tagliavini, Dimitrios Stathis, Ahmed Hemani:
Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms. ICECS 2023: 1-8 - [c119]Jiawei Xu, Yi Zheng, Chenxu Sheng, Yichen Cai, Dimitrios Stathis, Ruisi Shen, Lirong Zheng, Zhuo Zou, Laigui Hu, Ahmed Hemani:
Optoelectronic Memristor Model for Optical Synaptic Circuit of Spiking Neural Networks. NEWCAS 2023: 1-5 - [c118]Pudi Dhilleswararao, Vamsi Goudu, Srinivas Boppu, Ritika Ratnu, Ahmed Hemani:
Implementation of Image Averaging on DRRA and DiMArch Architectures. SBCCI 2023: 1-6 - [c117]Reeshita Kallapu, Dimitrios Stathis, Srinivas Boppu, Ahmed Hemani:
DRRA-based Reconfigurable Architecture for Mixed-Radix FFT. VLSID 2023: 25-30 - 2022
- [j30]Nesma M. Rezk, Tomas Nordström, Dimitrios Stathis, Zain Ul-Abdin, Eren Erdal Aksoy, Ahmed Hemani:
MOHAQ: Multi-Objective Hardware-Aware Quantization of recurrent neural networks. J. Syst. Archit. 133: 102778 (2022) - [c116]Deyu Wang, Jiawei Xu, Feng Li, Lianhao Zhang, Yuning Wang, Anders Lansner, Ahmed Hemani, Lirong Zheng, Zhuo Zou:
Memristor-Based In-Circuit Computation for Trace-Based STDP. AICAS 2022: 1-4 - [c115]Yu Yang, Dimitrios Stathis, Ahmed Hemani:
Reducing the Configuration Overhead of the Distributed Two-level Control System. DATE 2022: 104-107 - [i6]Yu Yang, Ahmed Hemani:
Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style. CoRR abs/2206.07984 (2022) - 2021
- [j29]Syed Mohammad Asad Hassan Jafri, Hasan Hassan, Ahmed Hemani, Onur Mutlu:
Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators. ACM Trans. Archit. Code Optim. 18(1): 2:1-2:29 (2021) - [c114]Jiawei Xu, Deyu Wang, Feng Li, Lianhao Zhang, Dimitrios Stathis, Yu Yang, Yi Jin, Anders Lansner, Ahmed Hemani, Zhuo Zou, Li-Rong Zheng:
A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation. AICAS 2021: 1-4 - [c113]Dimitrios Stathis, Yu Yang, Ahmed Hemani, Anders Lansner:
Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex. DATE 2021: 685-688 - [c112]Yu Yang, Ahmed Hemani, Kolin Paul:
Scheduling Persistent and Fully Cooperative Instructions. DSD 2021: 229-237 - [c111]Yu Yang, Ahmed Hemani, Kolin Paul:
Scheduling Persistent and Fully Cooperative Instructions. FCCM 2021: 274 - [c110]Jordi Altayó González, Dimitrios Stathis, Ahmed Hemani:
Synthesis of predictable global NoC by abutment in synchoros VLSI design. NOCS 2021: 61-66 - [c109]Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani:
Clock Tree Generation by Abutment in Synchoros VLSI Design. NorCAS 2021: 1-7 - [c108]Ayazulla Khan Patan, Dimitrios Stathis, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani:
Design and Implementation of Optimized Register File for Streaming Applications. VDAT 2021: 1-4 - [i5]Nesma M. Rezk, Tomas Nordström, Dimitrios Stathis, Zain Ul-Abdin, Eren Erdal Aksoy, Ahmed Hemani:
Multi-objective Recurrent Neural Networks Optimization for the Edge - a Quantization-based Approach. CoRR abs/2108.01192 (2021) - [i4]Jordi Altayó González, Dimitrios Stathis, Ahmed Hemani:
Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design. CoRR abs/2108.12213 (2021) - 2020
- [j28]Ahmed Hemani, Muhammad Shafique, Kolin Paul:
Guest Editorial: Special Issue on Architectures and Design Methods for Neural Networks. J. Signal Process. Syst. 92(11): 1215-1217 (2020) - [j27]Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn:
eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. J. Signal Process. Syst. 92(11): 1323-1343 (2020) - [c107]Guido Baccelli, Dimitrios Stathis, Ahmed Hemani, Maurizio Martina:
NACU: A Non-Linear Arithmetic Unit for Neural Networks. DAC 2020: 1-6 - [c106]Lizheng Liu, Deyu Wang, Yuning Wang, Anders Lansner, Ahmed Hemani, Yu Yang, Xiaoming Hu, Zhuo Zou, Lirong Zheng:
A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network. NorCAS 2020: 1-6
2010 – 2019
- 2019
- [j26]Muhammad Ali Shami, Muhammad Adeel Tajammul, Ahmed Hemani:
Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays. J. Signal Process. Syst. 91(5): 459-473 (2019) - [c105]Dimitrios Stathis, Yu Yang, Saurabh Tewari, Ahmed Hemani, Kolin Paul, Manfred G. Grabherr, Rafi Ahmad:
Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps. ISVLSI 2019: 560-567 - [i3]Syed M. A. H. Jafri, Hasan Hassan, Ahmed Hemani, Onur Mutlu:
Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators. CoRR abs/1910.06672 (2019) - [i2]Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani:
Regional Clock Tree Generation by Abutment in Synchoros VLSI Design. CoRR abs/1910.11253 (2019) - [i1]Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Syed Mohammad Asad Hassan Jafri, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn:
eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. CoRR abs/1911.00889 (2019) - 2018
- [c104]Yu Yang, Dimitrios Stathis, Prashant Sharma, Kolin Paul, Ahmed Hemani, Manfred G. Grabherr, Rafi Ahmad:
RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform. SAMOS 2018: 105-114 - 2017
- [j25]Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn:
3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems. Int. J. Parallel Program. 45(6): 1420-1460 (2017) - [j24]Mohammad Badawi, Zhonghai Lu, Ahmed Hemani:
Quality-of-service-aware adaptation scheme for multi-core protocol processing architecture. Microprocess. Microsystems 54: 47-59 (2017) - [j23]Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn:
A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture. J. Signal Process. Syst. 87(3): 327-341 (2017) - [c103]Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Leonardo Intesa:
SPEED: Open-Source Framework to Accelerate Speech Recognition on Embedded GPUs. DSD 2017: 94-101 - [c102]Yu Yang, Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis:
MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to GPUs. PARMA-DITAM@HiPEAC 2017: 31-36 - [c101]Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Kolin Paul, Naeem Abbas:
MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks. IPDPS 2017: 276-286 - [c100]Syed Mohammad Asad Hassan Jafri, Nasim Farahini, Ahmed Hemani:
SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level. ISVLSI 2017: 25-31 - [c99]Ahmed Hemani, Syed Mohammad Asad Hassan Jafri, Shayesteh Masoumian:
Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable. NOCS 2017: 8:1-8:10 - [c98]Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis:
Can a reconfigurable architecture beat ASIC as a CNN accelerator? SAMOS 2017: 97-104 - 2016
- [j22]Jamshaid Sarwar Malik, Ahmed Hemani:
Gaussian Random Number Generation: A Survey on Hardware Architectures. ACM Comput. Surv. 49(3): 53:1-53:37 (2016) - [j21]Syed M. A. H. Jafri, Masoud Daneshtalab, Naeem Abbas, Guillermo Serrano Leon, Ahmed Hemani:
TransMap: Transformation Based Remapping and Parallelism for High Utilization and Energy Efficiency in CGRAs. IEEE Trans. Computers 65(11): 3456-3469 (2016) - [j20]Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Peeter Ellervee, Hannu Tenhunen:
Polymorphic Configuration Architecture for CGRAs. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 403-407 (2016) - [c97]Mohammad Badawi, Zhonghai Lu, Ahmed Hemani:
Elastic Management and QoS Provisioning Scheme for Adaptable Multi-core Protocol Processing Architecture. DSD 2016: 575-583 - [c96]Ahmed Hemani:
The SiLago Method: Next Generation VLSI Architectures and Design Methods. MES@ISCA 2016: 1 - [c95]Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Peeter Ellervee:
TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs. PATMOS 2016: 92-99 - [c94]Mohammad Badawi, Zhonghai Lu, Ahmed Hemani:
Service-Guaranteed Multi-port Packet Memory for Parallel Protocol Processing Architecture. PDP 2016: 408-412 - 2015
- [j19]Syed M. A. H. Jafri, Ozan Ozbag, Nasim Farahini, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs. ACM J. Emerg. Technol. Comput. Syst. 11(4): 40:1-40:29 (2015) - [j18]Syed M. A. H. Jafri, Masoud Daneshtalab, Ahmed Hemani, Naeem Abbas, Muhammad Ali Awan, Juha Plosila:
TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs. Microprocess. Microsystems 39(8): 973-986 (2015) - [j17]Jamshaid Sarwar Malik, Ahmed Hemani, Jameel Nawaz Malik, Ben Slimane, Nasirud Din Gohar:
Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 842-855 (2015) - [c93]Nasim Farahini, Ahmed Hemani:
Atomic stream computation unit based on micro-thread level parallelism. ASAP 2015: 25-29 - [c92]Tuan Ngyen, Syed M. A. H. Jafri, Masoud Daneshtalab, Ahmed Hemani, Sergei Dytckov, Juha Plosila, Hannu Tenhunen:
FIST: A Framework to Interleave Spiking Neural Networks on CGRAs. PDP 2015: 751-758 - [c91]Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Shuo Li:
Physical design aware system level synthesis of hardware. SAMOS 2015: 141-148 - [c90]Pei Liu, Ahmed Hemani, Kolin Paul:
3D-stacked many-core architecture for biological sequence analysis problems. SAMOS 2015: 211-220 - [c89]Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Peeter Ellervee, Ahmed Hemani, Hannu Tenhunen, Juha Plosila:
DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs. VLSID 2015: 547-552 - 2014
- [j16]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Private reliability environments for efficient fault-tolerance in CGRAs. Des. Autom. Embed. Syst. 18(3-4): 295-327 (2014) - [j15]Masoud Daneshtalab, Maurizio Palesi, Juha Plosila, Ahmed Hemani:
Special issue on many-core embedded systems. Microprocess. Microsystems 38(6): 525 (2014) - [j14]Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Kolin Paul:
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric. Microprocess. Microsystems 38(8): 788-802 (2014) - [j13]Jean-Michel Chabloz, Ahmed Hemani:
Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 641-654 (2014) - [c88]Mohammad Badawi, Ahmed Hemani, Zhonghai Lu:
Customizable coarse-grained energy-efficient reconfigurable packet processing architecture. ASAP 2014: 30-35 - [c87]Anders Lansner, Ahmed Hemani, Nasim Farahini:
Spiking brain models: Computation, memory and communication constraints for custom hardware implementation. ASP-DAC 2014: 556-562 - [c86]Nasim Farahini, Ahmed Hemani, Anders Lansner, Fabien Clermidy, Christer Svensson:
A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain. ASP-DAC 2014: 578-585 - [c85]Shuo Li, Ahmed Hemani:
Case Study: Constraint Programming in a System Level Synthesis Framework. CP 2014: 846-861 - [c84]Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen:
Morphable Compression Architecture for Efficient Configuration in CGRAs. DSD 2014: 42-49 - [c83]Shuo Li, Ahmed Hemani:
Three-Dimensional Design Space Exploration for System Level Synthesis. DSD 2014: 419-426 - [c82]Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen:
Customizable Compression Architecture for Efficient Configuration in CGRAs. FCCM 2014: 31 - [c81]Shuo Li, Ahmed Hemani:
Accurate and Efficient Three Level Design Space Exploration Based on Constraints Satisfaction Optimization Problem Solver. FCCM 2014: 174 - [c80]Syed M. A. H. Jafri, Guilermo Serrano, Masoud Daneshtalab, Naeem Abbas, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
TransPar: Transformation based dynamic Parallelism for low power CGRAs. FPL 2014: 1-8 - [c79]Syed M. A. H. Jafri, Tuan Nguyen Gia, Sergei Dytckov, Masoud Daneshtalab, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
NeuroCGRA: A CGRA with support for neural networks. HPCS 2014: 506-511 - [c78]Hassan Anwar, Syed M. A. H. Jafri, Sergei Dytckov, Masoud Daneshtalab, Masoumeh Ebrahimi, Ahmed Hemani, Juha Plosila, Giovanni Beltrame, Hannu Tenhunen:
Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures. MES 2014: 64-67 - [c77]Pei Liu, Ahmed Hemani, Kolin Paul:
A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture. ISSoC 2014: 1-8 - [c76]Siavoosh Payandeh Azad, Nasim Farahini, Ahmed Hemani:
Customization methodology of a Coarse Grained Reconfigurable architecture. NORCHIP 2014: 1-4 - [c75]Syed M. A. H. Jafri, Guilermo Serrano, Junaid Iqbal, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs. ICSAMOS 2014: 233-241 - 2013
- [j12]Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes. Microprocess. Microsystems 37(8-A): 811-822 (2013) - [j11]Iraklis Anagnostopoulos, Jean-Michel Chabloz, Ioannis Koutras, Alexandros Bartzas, Ahmed Hemani, Dimitrios Soudris:
Power-aware dynamic memory management on many-core platforms utilizing DVFS. ACM Trans. Embed. Comput. Syst. 13(1s): 40:1-40:25 (2013) - [c74]Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
Private configuration environments (PCE) for efficient reconfiguration, in CGRAs. ASAP 2013: 227-236 - [c73]Jamshaid Sarwar Malik, Ahmed Hemani, Nasirud Din Gohar:
Unifying CORDIC and Box-Muller algorithms: An accurate and efficient Gaussian Random Number generator. ASAP 2013: 277-280 - [c72]Shuo Li, Nasim Farahini, Ahmed Hemani, Kathrin Rosvall, Ingo Sander:
System level synthesis of hardware for DSP applications using pre-characterized function implementations. CODES+ISSS 2013: 16:1-16:10 - [c71]Shuo Li, Ahmed Hemani:
Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework. DSD 2013: 11-17 - [c70]Nasim Farahini, Ahmed Hemani, Kolin Paul:
Distributed Runtime Computation of Constraints for Multiple Inner Loops. DSD 2013: 389-395 - [c69]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. DSD 2013: 525-534 - [c68]Shuo Li, Nasim Farahini, Ahmed Hemani:
Global Control and Storage Synthesis for a System Level Synthesis Approach. FCCM 2013: 239 - [c67]Shuo Li, Jamshaid Sarwar Malik, Shaoteng Liu, Ahmed Hemani:
A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA. MES 2013: 25-32 - [c66]Nasim Farahini, Shuo Li, Muhammad Adeel Tajammul, Muhammad Ali Shami, Guo Chen, Ahmed Hemani, Wei Ye:
39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation. ISCAS 2013: 1448-1451 - [c65]U. Nidhi, Kolin Paul, Ahmed Hemani, Anshul Kumar:
High performance 3D-FFT implementation. ISCAS 2013: 2227-2230 - [c64]Syed M. A. H. Jafri, Ozan Bag, Ahmed Hemani, Nasim Farahini, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells. ISQED 2013: 104-111 - [c63]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Implementation and evaluation of configuration scrubbing on CGRAs: A case study. ISSoC 2013: 1-8 - [c62]Shuo Li, Ahmed Hemani:
Memory allocation and optimization in system-level architectural synthesis. ReCoSoC 2013: 1-7 - [c61]Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs. ICSAMOS 2013: 104-112 - [e1]Masoud Daneshtalab, Ahmed Hemani, Maurizio Palesi:
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, MES'2013, Held in conjunction with the 40th Annual IEEE/ACM International Symposium on Computer Architecture, ISCA 2013, June 24, 2013. ACM 2013, ISBN 978-1-4503-2063-4 [contents] - 2012
- [j10]Jamshaid Sarwar Malik, Paolo Palazzari, Ahmed Hemani:
Effort, resources, and abstraction vs performance in high-level synthesis: finding new answers to an old question. SIGARCH Comput. Archit. News 40(5): 64-69 (2012) - [c60]Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes. DSD 2012: 242-249 - [c59]Muhammad Ali Shami, Ahmed Hemani:
Classification of Massively Parallel Computer Architectures. IPDPS Workshops 2012: 344-351 - [c58]Pei Liu, Ahmed Hemani, Kolin Paul:
Improved Bioinformatics Processing Unit for Multiple Applications. IPDPS Workshops 2012: 390-396 - [c57]Muhammad Adeel Tajammul, Muhammad Ali Shami, Ahmed Hemani:
Segmented Bus Based Path Setup Scheme for a Distributed Memory Architecture. MCSoC 2012: 67-74 - [c56]Syed M. A. H. Jafri, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, Hannu Tenhunen:
Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation. PECCS 2012: 450-458 - [c55]Omer Malik, Ahmed Hemani:
A pragma based approach for mapping MATLAB applications on a coarse grained reconfigurable architecture. SBCCI 2012: 1-6 - [c54]Jean-Michel Chabloz, Ahmed Hemani:
Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links. VLSI Design 2012: 191-196 - 2011
- [j9]Haider Abbas, Christer Magnusson, Louise Yngström, Ahmed Hemani:
Addressing Dynamic Issues in Information Security Management. Inf. Manag. Comput. Secur. 19(1): 5-24 (2011) - [c53]Muhammad Ali Shami, Ahmed Hemani:
Address generation scheme for a coarse grain reconfigurable architecture. ASAP 2011: 17-24 - [c52]Sandro Penolazzi, Ingo Sander, Ahmed Hemani:
Predicting bus contention effects on energy and performance in multi-processor SoCs. DATE 2011: 1196-1199 - [c51]Fahimeh Jafari, Shuo Li, Ahmed Hemani:
Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture. DSD 2011: 73-80 - [c50]Jean-Michel Chabloz, Ahmed Hemani:
Low-Latency and Low-Overhead Mesochronous and Plesiochronous Synchronizers. DSD 2011: 157-164 - [c49]Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures. FPT 2011: 1-6 - [c48]Jean-Michel Chabloz, Ahmed Hemani:
A GALS Network-on-Chip based on rationally-related frequencies. ICCD 2011: 12-18 - [c47]Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures. IPDPS Workshops 2011: 290-293 - [c46]Jamshaid Sarwar Malik, Jameel Nawaz Malik, Ahmed Hemani, Nasirud Din Gohar:
An efficient hardware implementation of high quality AWGN generator using Box-Muller method. ISCIT 2011: 449-454 - [c45]Mohammad Badawi, Ahmed Hemani:
A coarse-grained reconfigurable protocol processor. SoC 2011: 102-107 - [c44]Omer Malik, Ahmed Hemani:
Synchronizing distributed state machines in a coarse grain reconfigurable architecture. SoC 2011: 128-135 - [c43]Pei Liu, Fatemeh O. Ebrahim, Ahmed Hemani, Kolin Paul:
A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics. ReConFig 2011: 190-197 - [c42]Jamshaid Sarwar Malik, Jameel Nawaz Malik, Ahmed Hemani, Nasirud Din Gohar:
Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theorem. VLSI-SoC 2011: 60-65 - [c41]Omer Malik, Ahmed Hemani, Muhammad Ali Shami:
A Library Development Framework for a Coarse Grain Reconfigurable Architecture. VLSI Design 2011: 153-158 - [c40]Pei Liu, Ahmed Hemani, Kolin Paul:
A Reconfigurable Processor for Phylogenetic Inference. VLSI Design 2011: 226-231 - [c39]Muhammad Adeel Tajammul, Muhammad Ali Shami, Ahmed Hemani, Sridharan Moorthi:
NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture. VLSI Design 2011: 232-237 - 2010
- [c38]Sandro Penolazzi, Ingo Sander, Ahmed Hemani:
Predicting energy and performance overhead of Real-Time Operating Systems. DATE 2010: 15-20 - [c37]Jean-Michel Chabloz, Ahmed Hemani:
Lowering the latency of interfaces for rationally-related frequencies. ICCD 2010: 23-30 - [c36]Jean-Michel Chabloz, Ahmed Hemani:
Distributed DVFS using rationally-related frequencies and discrete voltage levels. ISLPED 2010: 247-252 - [c35]Jamshaid Sarwar Malik, Ben Slimane, Ahmed Hemani, Nasirud Din Gohar:
Improving performance of fading channel simulators by use of uniformly distributed random numbers. ISSPIT 2010: 91-96 - [c34]Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin:
The MOSART Mapping Optimization for Multi-Core ARchiTectures. ISVLSI (Selected papers) 2010: 181-195 - [c33]Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin:
Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. ISVLSI 2010: 518-523 - [c32]Pei Liu, Ahmed Hemani:
A Coarse Grain Reconfigurable Architecture for sequence alignment problems in bio-informatics. SASP 2010: 50-57 - [c31]Muhammad Ali Shami, Ahmed Hemani:
Control Scheme for a CGRA. SBAC-PAD 2010: 17-24 - [c30]Sandro Penolazzi, Ingo Sander, Ahmed Hemani:
Inferring Energy and Performance Cost of RTOS in Priority-Driven Scheduling. SIES 2010: 1-8
2000 – 2009
- 2009
- [j8]Sandro Penolazzi, Ahmed Hemani, Luca Bolognino:
A General Approach to High-Level Energy and Performance Estimation in System-on-Chip Architectures. J. Low Power Electron. 5(3): 373-384 (2009) - [c29]Sandro Penolazzi, Luca Bolognino, Ahmed Hemani:
Energy and Performance Model of a SPARC Leon3 Processor. DSD 2009: 651-656 - [c28]Haider Abbas, Louise Yngström, Ahmed Hemani:
Option Based Evaluation: Security Evaluation of IT Products Based on Options Theory. ECBS-EERC 2009: 134-141 - [c27]Jean-Michel Chabloz, Ahmed Hemani:
A flexible communication scheme for rationally-related clock frequencies. ICCD 2009: 109-116 - [c26]Haider Abbas, Louise Yngström, Ahmed Hemani:
Adaptability infrastructure for bridging IT security evaluation and options theory. SIN 2009: 39-45 - [c25]Muhammad Ali Shami, Ahmed Hemani:
Morphable DPU: Smart and efficient data path for signal processing applications. SiPS 2009: 167-172 - [c24]Sandro Penolazzi, Ahmed Hemani, Luca Bolognino:
A General Approach to High-Level Energy and Performance Estimation in SoCs. VLSI Design 2009: 200-205 - 2002
- [j7]Chantal Ykman-Couvreur, Jurgen Lambrecht, Diederik Verkest, Francky Catthoor, Bengt Svantesson, Ahmed Hemani, F. Wolf:
Dynamic memory management methodology applied to embedded telecom network systems. IEEE Trans. Very Large Scale Integr. Syst. 10(5): 650-667 (2002) - [c23]Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani:
A Network on Chip Architecture and Design Methodology. ISVLSI 2002: 117-124 - 2001
- [j6]Johnny Öberg, Mattias O'Nils, Axel Jantsch, Adam Postula, Ahmed Hemani:
Grammar-based design of embedded systems. J. Syst. Archit. 47(3-4): 225-240 (2001) - [j5]Peeter Ellervee, Miguel Miranda, Francky Catthoor, Ahmed Hemani:
System-level data-format exploration for dynamically allocated datastructures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1469-1472 (2001) - [c22]Simon Leung, Adam Postula, Ahmed Hemani:
Test Strategies on Functionally Partitioned Module-Based Programmable Architecture for Base-Band Processing. DSD 2001: 326-335 - [c21]Abhijit K. Deb, Ahmed Hemani, Johnny Öberg, Adam Postula, Dan Lindqvist:
Hardware Software Codesign of DSP System Using Grammar Based Approach. VLSI Design 2001: 42-47 - 2000
- [j4]Ahmed Hemani, Abhijit K. Deb, Johnny Öberg, Adam Postula, Dan Lindqvist, Björn Fjellborg:
System Level Virtual Prototyping of DSP SOCs Using Grammar Based Approach. Des. Autom. Embed. Syst. 5(3-4): 295-311 (2000) - [j3]Axel Jantsch, Shashi Kumar, Ahmed Hemani:
A Metamodel for Studying Concepts in Electronic System Design. IEEE Des. Test Comput. 17(3): 78-85 (2000) - [j2]Johnny Öberg, Anshul Kumar, Ahmed Hemani:
Grammar-based hardware synthesis from port-size independent specifications. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 184-194 (2000) - [c20]Peeter Ellervee, Miguel Miranda, Francky Catthoor, Ahmed Hemani:
System-level data format exploration for dynamically allocated data structures. DAC 2000: 556-559 - [c19]Simon Leung, Adam Postula, Ahmed Hemani:
Development of Programmable Architecture for Base-Band Processing. EUROMICRO 2000: 1362-1367 - [c18]Simon Leung, Adam Postula, Ahmed Hemani:
Reconfigurable Architecture for Base-band Data Processing. PDPTA 2000
1990 – 1999
- 1999
- [c17]Ahmed Hemani, Thomas Meincke, Shashi Kumar, Adam Postula, Thomas Olsson, Peter Nilsson, Johnny Öberg, Peeter Ellervee, Dan Lundqvist:
Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style. DAC 1999: 873-878 - [c16]Axel Jantsch, Shashi Kumar, Ahmed Hemani:
The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems. DATE 1999: 256-262 - [c15]Peeter Ellervee, Ahmed Hemani, Miguel Miranda, Francky Catthoor:
Exploiting Data Transfer Locality in Memory Mapping. EUROMICRO 1999: 1014-1021 - [c14]Thomas Meincke, Ahmed Hemani, Shashi Kumar, Peeter Ellervee, Johnny Öberg, Thomas Olsson, Peter Nilsson, Dan Lindqvist, Hannu Tenhunen:
Globally asynchronous locally synchronous architecture for large high-performance ASICs. ISCAS (2) 1999: 512-515 - [c13]Ahmed Hemani, Johnny Öberg, Abhijit K. Deb, Dan Lindqvist, Björn Fjellborg:
System Level Virtual Prototyping of DSP ASICs Using Grammar Based Approach. IEEE International Workshop on Rapid System Prototyping 1999: 166-171 - 1998
- [c12]Johnny Öberg, Ahmed Hemani, Anshul Kumar:
Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols. DATE 1998: 596-603 - [c11]Johnny Öberg, Anshul Kumar, Ahmed Hemani:
Specification of Exception Handling in Grammar-Based Hardware Synthesis. EUROMICRO 1998: 10038-10041 - [c10]Bengt Svantesson, Shashi Kumar, Ahmed Hemani:
A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL. VLSI Design 1998: 78-84 - 1997
- [c9]Lars Hellberg, Ahmed Hemani, Jouni Isoaho, Axel Jantsch, Mehran Mokhtari, Hannu Tenhunen:
System oriented VLSI curriculum at KTH. MSE 1997: 57-59 - 1996
- [c8]Kalle Tammemäe, Mattias O'Nils, Ahmed Hemani:
Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems. FPL 1996: 193-199 - [c7]Johnny Öberg, Anshul Kumar, Ahmed Hemani:
Grammar-Based Hardware Synthesis of Data Communication Protocols. ISSS 1996: 14-19 - [c6]Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen:
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. VLSI Design 1996: 23-28 - [c5]Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani:
A Rule-Based Approach for Improving Allocation of Filter Structures in HLS. VLSI Design 1996: 133-139 - 1994
- [c4]Axel Jantsch, Peeter Ellervee, Ahmed Hemani, Johnny Öberg, Hannu Tenhunen:
Hardware/software partitioning and minimizing memory interface traffic. EURO-DAC 1994: 226-231 - [c3]Ahmed Hemani, Börje Karlsson, Mats Fredriksson, Kurt Nordqvist, Björn Fjellborg:
Application of High-Level Synthesis in an Industrial Project. VLSI Design 1994: 5-10 - 1993
- [c2]Ahmed Hemani:
Self-Organization and its Application to Binding. VLSI Design 1993: 186-191 - 1990
- [j1]Ahmed Hemani, Adam Postula:
Cell placement by self-organisation. Neural Networks 3(4): 377-383 (1990) - [c1]Ahmed Hemani, Adam Postula:
A neural net based self organising scheduling algorithm. EURO-DAC 1990: 136-140
Coauthor Index
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