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ORCIDAnis Uzzaman
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2010 – 2019
- 2010
[j2]Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki:
Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. IEICE Trans. Inf. Syst. 93-D(1): 17-23 (2010)
2000 – 2009
- 2009
- [j1]Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai:
Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electron. 5(4): 520-528 (2009) - [c14]Anis Uzzaman:
Is Low Power Testing Necessary? What does the Test Industry Truly Need?. Asian Test Symposium 2009: 215-216 - [c13]Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman:
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium 2009: 295-300 - [c12]Brion L. Keller, Dale Meehl, Anis Uzzaman, Richard Billings:
A Partially-Exhaustive Gate Transition Fault Model. Asian Test Symposium 2009: 361-364 - 2008
- [c11]Brion L. Keller, Sandeep Bhatia, Thomas Bartenstein, Brian Foutz, Anis Uzzaman:
Optimizing Test Data Volume Using Hybrid Compression. ATS 2008: 157-162 - [c10]Anis Uzzaman:
How To Increase the Effectiveness of Yield Diagnostics-Is DFM the Answer to This? ATS 2008: 221 - 2007
- [c9]Brion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen:
Using Programmable On-Product Clock Generation (OPCG) for Delay Test. ATS 2007: 69-72 - [c8]Brion L. Keller, Tom Jackson, Anis Uzzaman:
A Review of Power Strategies for DFT and ATPG. ATS 2007: 213 - [c7]Anis Uzzaman, Fidel Muradali, Takashi Aikyo, Robert C. Aitken, Tom Jackson, Rajesh Galivanche, Takeshi Onodera:
Test Roles in Diagnosis and Silicon Debug. ATS 2007: 367 - [c6]Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise:
Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. ITC 2007: 1-10 - 2006
- [c5]Anis Uzzaman, Brion L. Keller, Vivek Chickermane:
A Scalable Architecture for On-Chip Compression: Options and Trade-Offs. ATS 2006: 132 - [c4]Anis Uzzaman, Mick Tegethoff, Bibo Li, Kevin McCauley, Shuji Hamada, Yasuo Sato:
Not all Delay Tests Are the Same - SDQL Model Shows True-Time. ATS 2006: 147-152 - [c3]Sanae Seike, Ken Namura, Yukio Ohya, Anis Uzzaman, Shinichi Arima, Dale Meehl, Vivek Chickermane, Azumi Kobayashi, Satoshi Tanaka, Hiroyuki Adachi:
Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis. ATS 2006: 415-420 - 2005
- [c2]Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi:
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium 2005: 156-161 - [c1]Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman:
Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium 2005: 470
Coauthor Index
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