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ORCIDBiju K. Raveendran
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2020 – today
- 2024
[j9]Arun S. Nair, Geeta Patil, Archit Agarwal
, Aboli Vijayan Pai, Biju K. Raveendran, Sasikumar Punnekkat:
CAMP: a hierarchical cache architecture for multi-core mixed criticality processors. Int. J. Parallel Emergent Distributed Syst. 39(3): 317-352 (2024)- 2023
- [j8]Louella Colaco, Arun S. Nair, Biju K. Raveendran, Sasikumar Punnekkat:
Task models for mixed criticality systems - a review. Int. J. Crit. Comput. Based Syst. 10(4): 287-329 (2023) - [j7]Louella Colaco, Arun S. Nair, Anurag Madnawat, Biju K. Raveendran:
SACRED: Software Approach for Collaboration and Research Dissemination. Int. J. e Collab. 19(1): 1-20 (2023) - [j6]Louella Colaco, Prashiksha Jain, Arun S. Nair, Biju K. Raveendran, Sasikumar Punnekkat:
mcDVFS: cycle conserving DVFS scheduler for multi-core mixed criticality systems. Int. J. Parallel Emergent Distributed Syst. 38(5): 440-458 (2023) - 2021
- [c13]Arun S. Nair, Aboli Vijayan Pai, Biju K. Raveendran, Geeta Patil:
MOESIL: A Cache Coherency Protocol for Locked Mixed Criticality L1 Data Cache. DS-RT 2021: 1-8 - [c12]Louella Colaco, Amol Pai, Biju K. Raveendran, Sasikumar Punnekkat:
pmcEDF: An Energy Efficient Procrastination Scheduler for Multi-core Mixed Criticality Systems. HPCC/DSS/SmartCity/DependSys 2021: 727-732
2010 – 2019
- 2019
- [j5]Shubhangi K. Gawali, Biju K. Raveendran:
DPVFS: a dynamic procrastination cum DVFS scheduler for multi-core hard real-time systems. Int. J. Embed. Syst. 11(4): 461-471 (2019) - [j4]Geeta Patil, Neethu Bal Mallya, Biju K. Raveendran:
MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation. Int. J. Embed. Syst. 11(4): 493-507 (2019) - [c11]Arun S. Nair, Louella Mesquita Colaco, Geeta Patil, Biju K. Raveendran, Sasikumar Punnekkat:
MEDIATOR - A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems. DS-RT 2019: 1-8 - 2018
- [c10]Alen Sabu, Biju K. Raveendran, Rituparna Ghosh:
SMILEY: A Mixed-Criticality Real-Time Task Scheduler for Multicore Systems. DS-RT 2018: 55-62 - 2017
- [j3]Biju K. Raveendran, Pravin Joshi, Sahil Mittal:
eduCloud: a VM communication aware, migration efficient cloud for scientific computing. Int. J. Commun. Networks Distributed Syst. 18(3/4): 329-352 (2017) - [j2]Mayuri Digalwar, Praveen Gahukar, Biju K. Raveendran, Sudeept Mohan:
Energy efficient real-time scheduling algorithm for mixed task set on multi-core processors. Int. J. Embed. Syst. 9(6): 523-534 (2017) - [j1]Mayuri Digalwar, Biju K. Raveendran, Sudeept Mohan:
LAMCS: A leakage aware DVFS based mixed task set scheduler for multi-core processors. Sustain. Comput. Informatics Syst. 15: 63-81 (2017) - [c9]Kajal Varma, Geeta Patil, Biju K. Raveendran:
DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems. VLSID 2017: 207-212 - 2016
- [c8]Shubhangi K. Gawali, Biju K. Raveendran:
DPS: A dynamic procrastination scheduler for multi-core/multi-processor hard real time systems. CoDIT 2016: 286-291 - 2015
- [c7]Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran:
Simulation based Performance Study of Cache Coherence Protocols. iNIS 2015: 125-130 - [c6]Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran:
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors. VLSID 2015: 65-70
2000 – 2009
- 2008
- [c5]Biju K. Raveendran, Sundar Balasubramaniam, S. Gurunarayanan:
Evaluation of priority based real time scheduling algorithms: choices and tradeoffs. SAC 2008: 302-307 - 2007
- [c4]Biju K. Raveendran, Janardan Prasad Misra, Karan Bhatnagar, S. Gurunarayanan:
EFFS: Efficient Flash File System for Wireless Sensor Nodes. ESA 2007: 159-168 - [c3]Biju K. Raveendran, T. S. B. Sudarshan, Avinash Patil, Komal B. Randive, S. Gurunarayanan:
An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System. ESA 2007: 188-196 - 2006
- [c2]Biju K. Raveendran, Sundar Balasubramaniam, K. Durga Prasad, S. Gurunarayanan:
A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling. Asia-Pacific Computer Systems Architecture Conference 2006: 437-444 - [c1]Biju K. Raveendran, K. Durga Prasad, Sundar Balasubramaniam, S. Gurunarayanan:
Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems. ICDCN 2006: 466-478
Coauthor Index
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