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2010 – 2019
- 2019
[j10]I-Che Ou
, Jia-Ping Yang, Chia-Hung Liu, Kai-Jie Huang, Kun-Ju Tsai, Yu Lee, Yuan-Hua Chu, Yu-Te Liao:
A Sustainable Soil Energy Harvesting System With Wide-Range Power-Tracking Architecture. IEEE Internet Things J. 6(5): 8384-8392 (2019)- 2018
- [c26]I-Che Ou, Jia-Ping Yang, Chia-Hung Liu, Kai-Jie Huang, Kun-Ju Tsai, Yu Lee, Yuan-Hua Chu, Yu-Te Liao:
A Wide-Range Capacitive DC-DC Converter with 2D-MPPT for Soil/Solar Energy Extraction. A-SSCC 2018: 37-38 - [c25]Chao-Jen Huang, Yao-Sheng Ma, Wen-Hau Yang, Yen-Ting Lin, Chun-Chieh Kuo, Ke-Horng Chen, Hsiao-Jung Liu, Pei-Shan Yu, Fang-Chih Chu, Ching-Ju Lin, Hong-Wen Huang, Kuo-Chih Hung, Yuan-Hua Chu, Ying-Hsi Lin, Suhwan Kim, Krishnan Ravichandran:
A 99.2% Tracking Accuracy Single-Inductor Quadruple-Input-Quadruple-Output Buck-Boost Converter Topology with Periodical Interval Perturbation and Observation MPPT. A-SSCC 2018: 171-174 - [c24]Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Jia-Hung Peng, Yuan-Hua Chu:
MORAS: An energy-scalable system using adaptive voltage scaling. VLSI-DAT 2018: 1-4 - 2016
- [j9]Chia-Wen Chang, Kai-Yu Lo, Hossameldin A. Ibrahim, Ming-Chiuan Su, Yuan-Hua Chu, Shyh-Jye Jou:
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques. IEICE Trans. Electron. 99-C(4): 481-490 (2016) - [c23]Ting-Chou Lu, Li-Ren Huang, Yu Lee, Kun-Ju Tsai, Yu-Te Liao, Nai-Chen Cheng, Yuan-Hua Chu, Yi-Hsing Tsai, Fang-Chu Chen, Tzi-cker Chiueh:
Invited - Wireless sensor nodes for environmental monitoring in internet of things. DAC 2016: 3:1-3:5 - 2015
- [j8]Chia-Wen Chang, Yuan-Hua Chu, Shyh-Jye Jou:
A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications. IEICE Trans. Electron. 98-C(8): 882-891 (2015) - [c22]Chung-Shiang Wu, Kai-Chun Lin, Yi-Ping Kuo, Po-Hung Chen, Yuan-Hua Chu, Wei Hwang:
An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. ISCAS 2015: 1370-1373 - [c21]Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang:
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. VLSI-DAT 2015: 1-4 - 2014
- [j7]Shien-Chun Luo, Ching-Ji Huang, Yuan-Hua Chu:
A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1656-1665 (2014) - [j6]Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang:
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2578-2585 (2014) - [j5]Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu:
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. IEEE Trans. Circuits Syst. II Express Briefs 61-II(12): 947-951 (2014) - [c20]Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang:
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS. A-SSCC 2014: 361-364 - [c19]Chung-Hsun Huang, Wei-Jen Chen, Keng-Jui Chang, Yi-Hsuan Ting, Keng-Chang Hsu, Yu-Fu Pan, Chao-Chun Chen, Yuan-Hua Chu, Tay-Jyi Lin, Jinn-Shyan Wang:
Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET). Hot Chips Symposium 2014: 1 - [c18]Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou:
An ultra-low voltage hearing aid chip using variable-latency design technique. ISCAS 2014: 2543-2546 - [c17]Jen-Chieh Liu, Huan-Ke Chiu, Jia-Hung Peng, Yuan-Hua Chu, Hong-Yi Huang:
A radio-controlled receiver for clocks/watches and alarm applications. ISCAS 2014: 2672-2675 - [c16]Pei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang:
PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. SoCC 2014: 136-139 - 2013
- [j4]Meng-Fan Chang, Ming-Bin Chen, Lai-Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi:
A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques. IEEE J. Solid State Circuits 48(10): 2558-2569 (2013) - [j3]Shien-Chun Luo, Ching-Ji Huang, Yuan-Hua Chu:
An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library. IEEE Trans. Circuits Syst. II Express Briefs 60-II(10): 677-681 (2013) - [c15]Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang:
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159 - [c14]Mei-Wei Chen, Ming-Hung Chang, Pei-Chen Wu, Yi-Ping Kuo, Chun-Lin Yang, Yuan-Hua Chu, Wei Hwang:
A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range. SoCC 2013: 92-97 - 2012
- [c13]Tay-Jyi Lin, Yu-Ting Kuo, Yu-Jung Tsai, Ting-Yu Shyu, Yuan-Hua Chu:
Energy-efficient RISC design with on-demand circuit-level timing speculation. ASP-DAC 2012: 477-478 - [c12]Chao-Jen Huang, Wei-Chung Chen, Chia-Lung Ni, Ke-Horng Chen, Chien-Chun Lu, Yuan-Hua Chu, Ming-Ching Kuo:
Thermoelectric energy harvesting with 1mV low input voltage and 390nA quiescent current for 99.6% maximum power point tracking. ESSCIRC 2012: 105-108 - [c11]Weibo Hu, Yen-Ting Liu, Vighnesh Das, Cliff Schecht, Tam Q. Nguyen, Donald Y. C. Lie, Tzu-Chao Yan, Chien-Nan Kuo, Stanley Wu, Yuan-Hua Chu, Tzu-Yi Yang:
An ultra-low power interface CMOS IC design for biosensor applications. MWSCAS 2012: 1196-1199 - [c10]Mei-Wei Chen, Ming-Hung Chang, Yuan-Hua Chu, Wei Hwang:
An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation. SoCC 2012: 5-10 - [c9]Ming-Pin Chen, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Mon-Shu Ho, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi:
A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. VLSIC 2012: 112-113 - 2011
- [j2]Jui-Jen Wu, Yen-Hui Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi:
A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme. IEEE J. Solid State Circuits 46(4): 815-827 (2011) - [j1]David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq Kuen Lee, Yuan-Hua Chu, An-Yeu Wu:
Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. J. Signal Process. Syst. 62(3): 373-382 (2011) - [c8]Chia-Wen Chang, Shyh-Jye Jou, Yuan-Hua Chu:
0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations. ASICON 2011: 606-609 - 2010
- [c7]Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu:
Collaborative voltage scaling with online STA and variable-latency datapath. ACM Great Lakes Symposium on VLSI 2010: 347-352 - [c6]Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi:
A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications. ISSCC 2010: 266-267 - [c5]Yi-Hung Wei, Chuan-Yue Yang, Tei-Wei Kuo, Shih-Hao Hung, Yuan-Hua Chu:
Energy-efficient real-time scheduling of multimedia tasks on multi-core processors. SAC 2010: 258-262
2000 – 2009
- 2009
- [c4]Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao:
Full System Simulation and Verification Framework. IAS 2009: 165-168 - 2006
- [c3]Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu:
Design of STR level converters for SoCs using the multi-island dual-VDD design technique. ISCAS 2006 - 2005
- [c2]Wei-Bin Yang, Shu-Chang Kuo, Yuan-Hua Chu, Kuo-Hsing Cheng:
The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. ECCTD 2005: 193-196
1990 – 1999
- 1995
- [c1]Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu:
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS 1995: 1572-1575
Coauthor Index
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