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ORCIDJosé V. Busquets-Mataix
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2010 – 2019
- 2019
[j3]Carlos Domínguez, Juan-Miguel Martinez-Rubio, José V. Busquets-Mataix
, Houcine Hassan:
Human-computer cooperation platform for developing real-time robotic applications. J. Supercomput. 75(4): 1849-1868 (2019)- 2011
- [c11]José V. Busquets-Mataix, Carlos Catalá, Antonio Martí Campoy:
Architecture Extensions for Efficient Management of Scratch-Pad Memory. PATMOS 2011: 43-52
2000 – 2009
- 2005
- [c10]Antonio Martí Campoy, Isabelle Puaut, Angel Perles Ivars, José V. Busquets-Mataix:
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison. ECRTS 2005: 49-56 - [c9]Antonio Martí Campoy, Eugenio Tamura, Sergio Sáez, Francisco Rodríguez, José V. Busquets-Mataix:
On Using Locking Caches in Embedded Real-Time Systems. ICESS 2005: 150-159 - 2003
- [c8]Antonio Martí Campoy, Sergio Sáez, Angel Perles, J. V. Busquets:
Schedulability Analysis in EDF Scheduler with Cache Memories. RTCSA 2003: 328-341 - 2000
- [j2]José V. Busquets-Mataix, Daniel Gil, Pedro J. Gil, Andy J. Wellings:
Techniques to increase the schedulable utilization of cache-based preemptive real-time systems. J. Syst. Archit. 46(4): 357-378 (2000)
1990 – 1999
- 1999
- [j1]José Carlos Campelo, Francisco Rodríguez, Alicia Rubio, Rafael Ors, Pedro J. Gil, Lenin Lemus, J. V. Busquets, José Albaladejo, Juan José Serrano:
Distributed industrial control systems: a fault-tolerant architecture. Microprocess. Microsystems 23(2): 103-112 (1999) - [c7]Daniel Gil, R. Martínez, J. V. Busquets, Juan Carlos Baraza, Pedro J. Gil:
Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System. EDCC 1999: 191-208 - 1998
- [c6]Daniel Gil, Juan Carlos Baraza, J. V. Busquets, Pedro J. Gil:
Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System. EUROMICRO 1998: 10418-10425 - 1997
- [c5]José V. Busquets-Mataix, Juan José Serrano, Andy J. Wellings:
Hybrid instruction cache partitioning for preemptive real-time systems. RTS 1997: 56-63 - 1996
- [c4]José V. Busquets-Mataix, Juan José Serrano, Rafael Ors Carot, Pedro J. Gil, Andrew J. Wellings:
Adding Instruction Cache Effect to an Exact Schedulability Analysis of Preemptive Real-Time Systems. RTS 1996: 271-276 - [c3]José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings:
Adding instruction cache effect to schedulability analysis of preemptive real-time systems. IEEE Real Time Technology and Applications Symposium 1996: 204-212 - [c2]José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings:
Using harmonic task-sets to increase the schedulable utilization of cache-based preemptive real-time systems. RTCSA 1996: 195-202 - 1995
- [c1]José V. Busquets-Mataix, Juan José Serrano:
The impact of extrinsic cache performance on predictability of real-time systems. RTCSA 1995: 8-15
Coauthor Index
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