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ORCIDJih-Ching Chiu
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2020 – today
- 2022
[c23]Jih-Ching Chiu, Yu-Quen Chen, Yi-Xiang Wang, Yung-Chi Liu:
Design and Implementation of the Optimized Computing Architecture for Matrix Decomposition Algorithms. ICS 2022: 447-459- [c22]Jih-Ching Chiu, Zhe-You Yan, Yung-Chi Liu:
Design and Implementation of the CNN Accelator Based on Multi-streaming SIMD Mechanisms. ICS 2022: 460-473 - [c21]Jih-Ching Chiu, Yan-Ting Wu, Yung-Chi Liu, Chi-Yang Hsieh:
Design and Implementation of the Link-List DMA Controller for High Bandwidth Data Streaming. ICS 2022: 474-486 - 2020
- [c20]Jih-Ching Chiu, Yu-Yi Wang, Wei-Yi Lin:
The Brain Memory Architecture HW/SW Co-Design Platform with Adaptive CNN Algorithm. ICS 2020: 197-202 - [c19]Jih-Ching Chiu, Jun-Jiang Chen, Kuan-Lun Su:
Design and Implement Robust Wireless Network Based on TCP Protocol. ICS 2020: 252-261 - [c18]Jih-Ching Chiu, Cheng-Lin Tsai, Zhi-Yu Lee:
Design and Implement Adaptive Tree Topology Mechanism For Wi-Fi Wireless Network. ICS 2020: 278-282 - [c17]Jih-Ching Chiu, Hao-Yu Tseng, Zhi-Yu Lee:
Design of Multidimension-media Streaming Protocol Based on RTSP. ICS 2020: 341-347
2010 – 2019
- 2018
- [c16]Yi-Xuan Lu, Jih-Ching Chiu, Shu-Jung Chao, Yong-Bin Ye:
Design of Instruction Analyzer with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture. ICS 2018: 3-19 - [c15]Tsung-Lin Lee, Jih-Ching Chiu, Yueh-Lin Li:
Adaptive Linked-List Mechanism for Wi-Fi Wireless Network. ICS 2018: 49-61 - [c14]Guan-Jen Huang, Jih-Ching Chiu, Yueh-Lin Li:
Design and Implementation of Tree Topology Algorithm for Power Line Communication Network. ICS 2018: 62-75 - 2014
- [c13]Jih-Ching Chiu, Chun-Yao Zheng, Yao-Chin Huang, Kai-Ming Yang:
Design and implementation of sequential repair and backup routing protocol for wireless mesh network. ICNC 2014: 1066-1070 - [c12]Jih-Ching Chiu, Wen-Shin Wang, Chien-Lung Chen:
Linked List Routing Algorithm with Wormhole Mechanism for Data Collecting Wireless Network. ICS 2014: 1665-1674 - 2013
- [j12]Jih-Ching Chiu, Kai-Ming Yang:
High-speed low-power multiplexer-based selector for priority policy. Comput. Electr. Eng. 39(2): 202-213 (2013) - [j11]Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou, Chih-Kang Wu:
A relation-exchanging buffering mechanism for instruction and data streaming. Comput. Electr. Eng. 39(4): 1129-1141 (2013) - [j10]Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou:
A hyperscalar dual-core architecture for embedded systems. Microprocess. Microsystems 37(8-B): 929-940 (2013) - [j9]Hsuan-Chang Lee, Jih-Ching Chiu, Ken-Huang Lin:
Two-Dimensional Interpolation-Assisted Channel Prediction for OFDM Systems. IEEE Trans. Broadcast. 59(4): 648-657 (2013) - 2012
- [c11]Jih-Ching Chiu, Kai-Ming Yang, Chen-Ang Wong:
Analytical Modeling for Multi-transaction Bus on Distributed Systems. ICA3PP (2) 2012: 1-9 - 2011
- [j8]Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen, Ding-Siang Su:
A Unitable Computing Architecture for Chip Multiprocessors. Comput. J. 54(12): 2033-2052 (2011) - 2010
- [j7]Jih-Ching Chiu, Kai-Ming Yang:
A Novel instruction stream buffer for VLIW architectures. Comput. Electr. Eng. 36(1): 190-198 (2010) - [j6]Jih-Ching Chiu, Ta-Li Yeh:
IRES: An integrated software and hardware interface framework for reconfigurable embedded system. IET Comput. Digit. Tech. 4(1): 27-37 (2010) - [j5]Jih-Ching Chiu, Yu-Liang Chou, Tseng-Kuei Lin:
The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA. J. Inf. Sci. Eng. 26(4): 1273-1288 (2010) - [j4]Jih-Ching Chiu, Yu-Liang Chou:
A multi-streaming SIMD multimedia computing engine. Microprocess. Microsystems 34(7-8): 247-258 (2010) - [c10]Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su:
A hyperscalar multi-core architecture. Conf. Computing Frontiers 2010: 77-78 - [c9]Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen:
Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture. ICPP 2010: 277-286
2000 – 2009
- 2009
- [c8]Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng:
A multi-streaming SIMD architecture for multimedia applications. Conf. Computing Frontiers 2009: 51-60 - [c7]Jih-Ching Chiu, Ta-Li Yeh, Mun-Kit Leong:
The Software and Hardware Integration Linker for Reconfigurable Embedded System. CSE (2) 2009: 520-525 - [c6]Jih-Ching Chiu, Kai-Ming Yang, Mu-Chi Chang:
The Rendezvous Mechanism for the Multi-core AMBA System. ICPP Workshops 2009: 574-578 - [c5]Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou:
Design of a novel SIMD architecture by fusing operations and registers. ICS 2009: 503-504 - 2008
- [j3]Jih-Ching Chiu, Yu-Liang Chou, Ren-Bang Lin:
The Multi-context Reconfigurable Processing Unit for Fine-grain Computing. J. Inf. Sci. Eng. 24(3): 965-979 (2008) - [c4]Jih-Ching Chiu, Yu-Liang Chou, Ta-Li Yeh, Tseng-Kuei Lin:
Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA. ACSAC 2008: 1-8 - 2005
- [c3]Jih-Ching Chiu, Ren-Bang Lin:
FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit. Asia-Pacific Computer Systems Architecture Conference 2005: 171-185 - 2003
- [j2]Yung-Cheng Ma, Jih-Ching Chiu, Tien-Fu Chen, Chung-Ping Chung:
Variable-size data item placement for load and storage balancing. J. Syst. Softw. 66(2): 157-166 (2003) - 2002
- [j1]Jih-Ching Chiu, Michael Jin-Yi Wang, Chung-Ping Chung:
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. J. Inf. Sci. Eng. 18(3): 393-409 (2002) - 2000
- [c2]Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung:
Design of Instruction Stream Buffer with Trace Support for X86 Processors. ICCD 2000: 294-299
1990 – 1999
- 1997
- [c1]Shyh-An Chi, R.-Ming Shiu, Jih-Ching Chiu, Si-En Chang, Chung-Ping Chung:
Instruction Cache Prefetching with Extended BTB. ICPADS 1997: 360-
Coauthor Index
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