default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDLaung-Terng Wang
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2010 – 2019
- 2017
[j22]Dong Xiang
, Xiaoqing Wen, Laung-Terng Wang:
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 942-953 (2017)- 2016
- [j21]Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang:
CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator. J. Electron. Test. 32(5): 625-638 (2016) - 2015
- [c37]Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang:
SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator. ATS 2015: 43-48 - 2014
- [j20]Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. 97-D(10): 2706-2718 (2014) - [c36]Kuan-Yu Liao, Po-Juei Chen, Ang-Feng Lin, James Chien-Mo Li, Michael S. Hsiao, Laung-Terng Wang:
GPU-based timing-aware test generation for small delay defects. ETS 2014: 1-2 - 2013
- [j19]Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte:
LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing. IEEE Des. Test 30(4): 60-70 (2013) - [j18]Hyoung-Kook Kim, Laung-Terng Wang, Yu-Liang Wu, Wen-Ben Jone:
Testing of Synchronizers in Asynchronous FIFO. J. Electron. Test. 29(1): 49-72 (2013) - [c35]Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium 2013: 19-24 - [c34]Kuen-Wei Yeh, Jiun-Lang Huang, Hao-Jan Chao, Laung-Terng Wang:
A circular pipeline processing based deterministic parallel test pattern generator. ITC 2013: 1-8 - [c33]Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang:
On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design 2013: 279-284 - 2012
- [j17]Dong Xiang, Zhen Chen, Laung-Terng Wang:
Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing. ACM Trans. Design Autom. Electr. Syst. 17(2): 18:1-18:24 (2012) - [j16]Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang:
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. 17(4): 48:1-48:16 (2012) - [c32]Kelvin Nelson, Jaga Shanmugavadivelu, Jayanth Mekkoth, Venkat Ghanta, Jun Wu, Fei Zhuang, Hao-Jan Chao, Shianling Wu, Jie Rao, Lizhen Yu, Laung-Terng Wang:
Physical-design-friendly hierarchical logic built-in self-test - A case study. ISQED 2012: 1-6 - [c31]Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On pinpoint capture power management in at-speed scan test generation. ITC 2012: 1-10 - 2011
- [j15]Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu:
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 455-463 (2011) - [c30]Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang:
A novel scan segmentation design method for avoiding shift timing failure in scan testing. ITC 2011: 1-8 - [c29]Laung-Terng Wang:
Luncheon Speaker: "Introduction to SoC testing". SoCC 2011: 256-257 - 2010
- [j14]Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang:
Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer. J. Electron. Test. 26(3): 367-392 (2010) - [j13]Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor:
High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. IEICE Trans. Inf. Syst. 93-D(1): 2-9 (2010) - [j12]Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone:
Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 299-312 (2010) - [c28]Lizhen Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang, Xiaoqing Wen:
Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs. DFT 2010: 331-339 - [c27]Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang:
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. DFT 2010: 358-366 - [c26]Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li:
CSER: BISER-based concurrent soft-error resilience. VTS 2010: 153-158
2000 – 2009
- 2009
- [j11]Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li:
Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Des. Test Comput. 26(1): 26-35 (2009) - [c25]Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, FeiFei Zhao, Laung-Terng Wang:
Logic BIST Architecture for System-Level Test and Diagnosis. Asian Test Symposium 2009: 21-26 - [c24]Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu:
Analysis of Resistive Bridging Defects in a Synchronizer. Asian Test Symposium 2009: 443-449 - [c23]Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang:
Analysis of Resistive Open Defects in a Synchronizer. DFT 2009: 164-172 - 2008
- [j10]Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu:
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. IEEE Des. Test Comput. 25(2): 122-130 (2008) - [j9]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electron. Test. 24(4): 379-391 (2008) - [c22]Shianling Wu, Hiroshi Furukawa, Boryau Sheu, Laung-Terng Wang, Hao-Jan Chao, Lizhen Yu, Xiaoqing Wen, Michio Murakami:
Practical Challenges in Logic BIST Implementation. ATS 2008: 265 - [c21]Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor:
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. ATS 2008: 397-402 - [c20]Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte:
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT 2008: 143-151 - [c19]Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li:
Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. ITC 2008: 1-9 - [p1]Laung-Terng Wang, Charles E. Stroud, Kwang-Ting (Tim) Cheng:
Logic Testing. Wiley Encyclopedia of Computer Science and Engineering 2008 - 2007
- [j8]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita:
A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Trans. Inf. Syst. 90-D(9): 1398-1405 (2007) - [c18]Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian:
Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. ATS 2007: 207 - [c17]Xiaoxin Fan, Yu Hu, Laung-Terng Wang:
An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing. ATS 2007: 341-348 - [c16]Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang:
A novel scheme to reduce power supply noise for high-quality at-speed scan testing. ITC 2007: 1-10 - [i1]B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu:
At-Speed Logic BIST for IP Cores. CoRR abs/0710.4645 (2007) - 2006
- [j7]Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Trans. Inf. Syst. 89-D(5): 1679-1686 (2006) - [j6]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita:
A Per-Test Fault Diagnosis Method Based on the X-Fault Model. IEICE Trans. Inf. Syst. 89-D(11): 2756-2765 (2006) - [c15]Yu Hu, Cheng Li, Jia Li, Yinhe Han, Xiaowei Li, Wei Wang, Hua-Wei Li, Laung-Terng Wang, Xiaoqing Wen:
Test data compression based on clustered random access scan. ATS 2006: 231-236 - [c14]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja:
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD 2006: 251-258 - [c13]Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu:
A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing. ITC 2006: 1-10 - [c12]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita:
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS 2006: 58-65 - 2005
- [j5]Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja:
Efficient Test Set Modification for Capture Power Reduction. J. Low Power Electron. 1(3): 319-330 (2005) - [c11]B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu:
At-Speed Logic BIST for IP Cores. DATE 2005: 860-861 - [c10]Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo:
At-Speed Logic BIST Architecture for Multi-Clock Designs. ICCD 2005: 475-478 - [c9]Shianling Wu, Laung-Terng Wang, Jin Woo Cho, Zhigang Jiang, Boryau Sheu:
Test compression and logic BIST at your fingertips. ITC 2005: 2 - [c8]Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang:
UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction. ITC 2005: 8 - [c7]Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
Low-capture-power test generation for scan-based at-speed testing. ITC 2005: 10 - [c6]Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
On Low-Capture-Power Test Generation for Scan Testing. VTS 2005: 265-270 - 2004
- [c5]Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
On per-test fault diagnosis using the X-fault model. ICCAD 2004: 633-640 - [c4]Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai:
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. ITC 2004: 916-925
1980 – 1989
- 1988
- [j4]Laung-Terng Wang, Edward J. McCluskey:
Linear Feedback Shift Register Design Using Cyclic Codes. IEEE Trans. Computers 37(10): 1302-1306 (1988) - [j3]Laung-Terng Wang, Edward J. McCluskey:
Hybrid designs generating maximum-length sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 91-99 (1988) - [j2]Laung-Terng Wang, Edward J. McCluskey:
Circuits for pseudoexhaustive test pattern generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10): 1068-1080 (1988) - 1986
- [j1]Laung-Terng Wang, Edward J. McCluskey:
Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique. IEEE Trans. Computers 35(4): 367-370 (1986) - [c3]Laung-Terng Wang, Edward J. McCluskey:
Circuits for Pseudo-Exhaustive Test Pattern Generation. ITC 1986: 25-37 - [c2]Laung-Terng Wang, Edward J. McCluskey:
A Hybrid Design of Maximum-Length Sequence Generators. ITC 1986: 38-47 - 1984
- [c1]Zuhi Sun, Laung-Terng Wang:
Self-Testing of Embedded RAMs. ITC 1984: 148-156
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-25 05:50 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
