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ORCIDSheldon B. Akers Jr.
Person information
- affiliation: General Electric Company, Syracuse, New York, USA
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1990 – 1999
- 1990
[c10]Sheldon B. Akers Jr., Sungju Park, Balakrishnan Krishnamurthy, Ashok Swaminathan:
Why is less information from logic simulation more useful in fault simulation? ITC 1990: 786-800
1980 – 1989
- 1989
- [j16]Sheldon B. Akers Jr., Balakrishnan Krishnamurthy:
Test counting: a tool for VLSI testing. IEEE Des. Test 6(5): 58-77 (1989) - [j15]Sheldon B. Akers Jr., Balakrishnan Krishnamurthy:
A Group-Theoretic Model for Symmetric Interconnection Networks. IEEE Trans. Computers 38(4): 555-566 (1989) - 1987
- [j14]Sheldon B. Akers Jr., Balakrishnan Krishnamurthy:
On Group Graphs and Their Fault Tolerance. IEEE Trans. Computers 36(7): 885-888 (1987) - [c9]Sheldon B. Akers Jr., Balakrishnan Krishnamurthy, Dov Harel:
The Star Graph: An Attractive Alternative to the n-Cube. ICPP 1987: 393-400 - 1986
- [c8]Sheldon B. Akers Jr., Balakrishnan Krishnamurthy:
: A Group Theoretic Model for Symmetric Interconnection Networks. ICPP 1986: 216-223 - 1984
- [j13]Balakrishnan Krishnamurthy, Sheldon B. Akers Jr.:
On the Complexity of Estimating the Size of a Test Set. IEEE Trans. Computers 33(8): 750-753 (1984) - 1981
- [c7]Sheldon B. Akers Jr.:
On the use of the linear assignment algorithm in module placement. DAC 1981: 137-144 - 1980
- [j12]Sheldon B. Akers Jr.:
Test Generation Techniques. Computer 13(3): 9-15 (1980)
1970 – 1979
- 1978
- [j11]Sheldon B. Akers Jr.:
Binary Decision Diagrams. IEEE Trans. Computers 27(6): 509-516 (1978) - 1976
- [j10]Sheldon B. Akers Jr.:
A Logic System for Fault Test Generation. IEEE Trans. Computers 25(6): 620-630 (1976) - 1974
- [j9]Sheldon B. Akers Jr.:
Fault Diagnosis as a Graph Coloring Problem. IEEE Trans. Computers 23(7): 706-713 (1974) - 1973
- [j8]Sheldon B. Akers Jr.:
Universal Test Sets for Logic Networks. IEEE Trans. Computers 22(9): 835-839 (1973) - 1972
- [j7]Sheldon B. Akers Jr.:
A Rectangular Logic Array. IEEE Trans. Computers 21(8): 848-857 (1972) - [c6]Sheldon B. Akers Jr.:
Universal Test Sets for Logic Networks. SWAT 1972: 177-184 - 1971
- [c5]Sheldon B. Akers Jr.:
A Rectangular Logic Array. SWAT 1971: 79-90 - 1970
- [j6]Sheldon B. Akers Jr.:
R70-40 Module Clustering to Minimize Delay in Digital Networks. IEEE Trans. Computers 19(10): 987-988 (1970) - [c4]Sheldon B. Akers Jr., James M. Geyer, Donald L. Roberts:
IC mask layout with a single conductor layer. DAC 1970: 7-16
1960 – 1969
- 1968
- [j5]Sheldon B. Akers Jr.:
On Maximum Inversion with Minimum Inverters. IEEE Trans. Computers 17(2): 134-135 (1968) - 1965
- [j4]Sheldon B. Akers Jr.:
A Diagrammatic Approach to Multilevel Logic Synthesis. IEEE Trans. Electron. Comput. 14(2): 174-181 (1965) - [j3]Sheldon B. Akers Jr.:
On the Construction of (d, k) Graphs. IEEE Trans. Electron. Comput. 14(3): 488 (1965) - 1964
- [c3]Sheldon B. Akers Jr.:
A diagrammatic approach to multi-level logic synthesis. SWCT 1964: 165-173 - 1962
- [c2]Sheldon B. Akers Jr.:
Synthesis of combinational logic using three-input majority gates. SWCT 1962: 149-157 - 1961
- [j2]Sheldon B. Akers Jr.:
A Truth Table Method for the Synthesis of Combinational Logic. IRE Trans. Electron. Comput. 10(4): 604-615 (1961) - [c1]Sheldon B. Akers Jr.:
Threshold logic and two-person, zero-sum games. SWCT 1961: 27-33
1950 – 1959
- 1955
- [j1]Sheldon B. Akers Jr., Joyce Friedman:
A Non-Numerical Approach to Production Scheduling Problems. Oper. Res. 3(4): 429-442 (1955)
Coauthor Index
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