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ORCIDJ. Paul Roth
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1980 – 1989
- 1986
[j10]J. Paul Roth:
Minimization by the D Algorithm. IEEE Trans. Computers 35(5): 476-478 (1986)- [c7]David M. Wu, Charles E. Radke, J. Paul Roth:
Statistical AC Test Coverage. ITC 1986: 538-541 - 1984
- [c6]J. Paul Roth, Vojin G. Oklobdzija, John F. Beetem:
Test Generation for FET Switching Circuits. ITC 1984: 59-62 - [c5]J. Paul Roth:
VLSI Verification and Correction. VLSI Engineering 1984: 174-176
1970 – 1979
- 1978
- [j9]J. Paul Roth:
Programmed Logic Array Optimization. IEEE Trans. Computers 27(2): 174-176 (1978) - 1977
- [j8]J. Paul Roth:
Hardware Verification. IEEE Trans. Computers 26(12): 1292-1294 (1977) - 1972
- [c4]J. Paul Roth:
Design of diagnosible automata. ACM Annual Conference (1) 1972: 368 - 1971
- [j7]Gianfranco R. Putzolu, J. Paul Roth:
A Heuristic Algorithm for the Testing of Asynchronous Circuits. IEEE Trans. Computers 20(6): 639-647 (1971) - [j6]Willard G. Bouricius, Edward P. Hsieh, Gianfranco R. Putzolu, J. Paul Roth, Peter R. Schneider, Chung-Jen Tan:
Algorithms for Detection of Faults in Logic Circuits. IEEE Trans. Computers 20(11): 1258-1264 (1971) - 1970
- [j5]J. Paul Roth:
R70-12 Diagnosis of Single-Gate Failures in Combinational Circuits. IEEE Trans. Computers 19(6): 564-565 (1970)
1960 – 1969
- 1967
- [j4]J. Paul Roth, Willard G. Bouricius, Peter R. Schneider:
Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits. IEEE Trans. Electron. Comput. 16(5): 567-580 (1967) - 1965
- [c3]J. Paul Roth:
Systematic design of automata. AFIPS Fall Joint Computing Conference (1) 1965: 1093-1100 - 1962
- [j3]J. Paul Roth, Richard M. Karp:
Minimization Over Boolean Graphs. IBM J. Res. Dev. 6(2): 227-238 (1962) - 1961
- [c2]J. M. Galey, R. E. Norby, J. Paul Roth:
Techniques for the diagnosis of switching circuit failures. SWCT 1961: 152-160 - [c1]Richard M. Karp, F. E. McFarlin, J. Paul Roth, J. R. Wilts:
A computer program for the synthesis of combinational switching circuits. SWCT 1961: 182-194 - 1960
- [j2]J. Paul Roth:
Minimization over Boolean Trees. IBM J. Res. Dev. 4(5): 543-558 (1960)
1950 – 1959
- 1959
- [j1]J. Paul Roth, Eric G. Wagner:
Algebraic Topological Methods for the Synthesis of Switching Systems - Part III: Minimization of Nonsingular Boolean Trees. IBM J. Res. Dev. 3(4): 326-344 (1959)
Coauthor Index
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