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2020 – today
- 2024
[j41]Yee-Yang Tee
, Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee:
Integrated Circuit Mask-Generative Adversarial Network for Circuit Annotation With Targeted Data Augmentation. IEEE Intell. Syst. 39(1): 37-45 (2024)- [j40]Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Kwen-Siong Chong, Bah-Hwee Gwee:
Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1959-1963 (2024) - [c84]Juncheng Chen, Han Zhang, Zishuo Yang, Yicheng Xu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee:
A Novel Non-profiling Side-Channel Attack on Masked Devices with Connectivity Matrix. ISCAS 2024: 1-5 - [c83]Xuenong Hong, Zilong Hu, Han Zhang, Yee-Yang Tee, Tong Lin, Yiqiong Shi, Deruo Cheng, Bah-Hwee Gwee:
MLConnect: A Machine Learning Based Connection Prediction Framework for Error Correction in Recovered Circuit. ISCAS 2024: 1-5 - [c82]Yuzhou Tong, Yongming Chen, Bah-Hwee Gwee, Qi Cao, Sirajudeen Gulam Razul, Zhiping Lin:
A Method for Out-of-Distribution Detection in Encrypted Mobile Traffic Classification. ISCAS 2024: 1-5 - 2023
- [j39]Xuenong Hong, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee:
GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning. IEEE Trans. Artif. Intell. 4(5): 1199-1213 (2023) - [j38]Yee-Yang Tee, Xuenong Hong, Deruo Cheng, Chye-Soon Chee, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee:
Patch-Based Adversarial Training for Error-Aware Circuit Annotation of Delayered IC Images. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3694-3698 (2023) - [c81]Deruo Cheng, Yiqiong Shi, Yee-Yang Tee, Jingsi Song, Xue Wang, Bihan Wen, Bah-Hwee Gwee:
Deep-learning-based X-ray CT Slice Analysis for Layout Verification in Printed Circuit Boards. AICAS 2023: 1-5 - [c80]Erdong Huang, Xuenong Hong, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee:
GRACER: Graph-Based Standard Cell Recognition in IC Images for Hardware Assurance. IECON 2023: 1-6 - [c79]Tong Lin, Yiqiong Shi, Bah-Hwee Gwee:
SEM2GDS: A Deep-Learning Based Framework To Detect Malicious Modifications In IC Layout. ISCAS 2023: 1-5 - [c78]Yongming Chen, Yuzhou Tong, Bah-Hwee Gwee, Qi Cao, Sirajudeen Gulam Razul, Zhiping Lin:
Real-time Traffic Classification in Encrypted Wireless Communication Network. ISCAS 2023: 1-5 - [c77]Jinhen Lee, Victor Adrian, Sun-Yang Tay, Yanshan Xie, Bah-Hwee Gwee, Joseph S. Chang:
A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters. ISCAS 2023: 1-5 - [c76]Jun-Sheng Ng, Juncheng Chen, Si Wu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee:
Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs. ISCAS 2023: 1-5 - [c75]Zixiang Zhou, Lei Sun, Hangcheng Han, Juncheng Chen, Bah-Hwee Gwee, Zhiping Lin:
A Residual-Remainder Coupled Unlimited Sampling Framework for High Dynamic Range Signal Conversion. ISCAS 2023: 1-5 - 2022
- [j37]Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh:
Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision. IET Circuits Devices Syst. 16(2): 169-177 (2022) - [j36]Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee:
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1144-1157 (2022) - [c74]Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Zhili Zou, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee:
Incremental Linear Regression Attack. AsianHOST 2022: 1-4 - [c73]Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee:
Non-profiling based Correlation Optimization Deep Learning Analysis. ISCAS 2022: 2246-2250 - [c72]Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee:
An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. ISCAS 2022: 2256-2260 - [c71]Sun-Yang Tay, Victor Adrian, Joseph S. Chang, Jinhen Lee, Bah-Hwee Gwee:
A Versatile and Accurate Vector-Based Method for Modeling and Analyzing Planar Air-Core Inductors. ISCAS 2022: 3063-3067 - [i1]Yee-Yang Tee, Deruo Cheng, Chye-Soon Chee, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee:
Unsupervised Domain Adaptation with Histogram-gated Image Translation for Delayered IC Image Analysis. CoRR abs/2209.13479 (2022) - 2021
- [j35]Kwen-Siong Chong, Jun-Sheng Ng, Juncheng Chen, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Joseph Sylvester Chang, Bah-Hwee Gwee:
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 343-356 (2021) - [j34]Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee:
A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 2122-2126 (2021) - [j33]Juncheng Chen, Jun-Sheng Ng, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee:
A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures. IEEE Trans. Inf. Forensics Secur. 16: 3767-3779 (2021) - [c70]Ling Huang, Deruo Cheng, Xulei Yang, Tong Lin, Yiqiong Shi, Kaiyi Yang, Bah-Hwee Gwee, Bihan Wen:
Joint Anomaly Detection and Inpainting for Microscopy Images Via Deep Self-Supervised Learning. ICIP 2021: 3497-3501 - [c69]Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee:
Normalized Differential Power Analysis - for Ghost Peaks Mitigation. ISCAS 2021: 1-5 - 2020
- [c68]Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee:
High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC. APCCAS 2020: 161-164 - [c67]Bah-Hwee Gwee:
Hardware Attack and Assurance with Machine Learning: A Security Threat to Circuits and Systems. APCCAS 2020: i - [c66]Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee:
A Secure Data-Toggling SRAM for Confidential Data Protection. ISCAS 2020: 1 - [c65]Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. ISCAS 2020: 1-5 - [c64]Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee:
A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES). ISCAS 2020: 1-5 - [c63]Weng-Geng Ho, Ali Akbar Pammu, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee:
High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications. ISOCC 2020: 173-174
2010 – 2019
- 2019
- [j32]Deruo Cheng, Yiqiong Shi, Bah-Hwee Gwee, Kar-Ann Toh, Tong Lin:
A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images. IEEE Intell. Syst. 34(2): 36-43 (2019) - [j31]Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee:
A Secure Data-Toggling SRAM for Confidential Data Protection. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4186-4199 (2019) - [j30]Ali Akbar Pammu, Kwen-Siong Chong, Yi Wang, Bah-Hwee Gwee:
A Highly Efficient Side Channel Attack with Profiling through Relevance-Learning on Physical Leakage Information. IEEE Trans. Dependable Secur. Comput. 16(3): 376-387 (2019) - [j29]Ali Akbar Pammu, Weng-Geng Ho, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee:
A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor. IEEE Trans. Inf. Forensics Secur. 14(4): 1023-1036 (2019) - [c62]Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang:
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. AsianHOST 2019: 1-7 - [c61]Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh:
Global Template Projection and Matching Method for Training-Free Analysis of Delayered IC Images. ISCAS 2019: 1-5 - [c60]Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, W. Shu, Joseph S. Chang, Bah-Hwee Gwee:
Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. ISCAS 2019: 1-5 - [c59]Weng-Geng Ho, Ali Akbar Pammu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee:
Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications. SoCC 2019: 86-91 - 2018
- [j28]Cui Keer, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang:
A Noise-Shaped Randomized Modulation for Switched-Mode DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 394-405 (2018) - [j27]Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh:
Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1849-1853 (2018) - [j26]Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang:
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 196-200 (2018) - [c58]Weng-Geng Ho, Zixian Zheng, Kwen-Siong Chong, Bah-Hwee Gwee:
A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation. DSP 2018: 1-5 - [c57]Xuenong Hong, Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee:
Deep Learning for Automatic IC Image Analysis. DSP 2018: 1-5 - 2017
- [j25]Kwen-Siong Chong, Weng-Geng Ho, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang:
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 402-415 (2017) - [c56]James Lim, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee:
DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer. ISCAS 2017: 1-4 - [c55]Qianqian Liu, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang:
A class-E RF power amplifier with a novel matching network for high-efficiency dynamic load modulation. ISCAS 2017: 1-4 - [c54]Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee:
Highly secured state-shift local clock circuit to countermeasure against side channel attack. ISCAS 2017: 1-4 - [c53]Cui Keer, Victor Adrian, Yin Sun, Bah-Hwee Gwee, Joseph S. Chang:
A low-harmonics low-noise randomized modulation scheme for multi-phase DC-DC converters. NEWCAS 2017: 165-168 - 2016
- [c52]Ali Akbar Pammu, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Nan Liu, Bah-Hwee Gwee:
Success rate model for fully AES-128 in correlation power analysis. APCCAS 2016: 115-118 - [c51]Ali Akbar Pammu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee:
Interceptive side channel attack on AES-128 wireless communications for IoT applications. APCCAS 2016: 650-653 - [c50]Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications. DATE 2016: 850-853 - [c49]Weng-Geng Ho, Kyaw Zwa Lwin Ne, N. Prashanth Srinivas, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee:
Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM. ISCAS 2016: 698-701 - [c48]Weng-Geng Ho, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. ISCAS 2016: 1762-1765 - [c47]Weng-Geng Ho, Ali Akbar Pammu, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee:
Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack. ISIC 2016: 1-4 - [c46]Qianqian Liu, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang:
A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled output matching network. ISIC 2016: 1-4 - [c45]Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee:
Highly secured arithmetic hiding based S-Box on AES-128 implementation. ISIC 2016: 1-4 - [c44]Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee:
Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture. NAS 2016: 1-7 - 2015
- [j24]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer. IET Circuits Devices Syst. 9(4): 309-318 (2015) - [c43]Hongxu Yin, Bah-Hwee Gwee, Zhiping Lin, Achanna Anil Kumar, Sirajudeen Gulam Razul, Chong Meng Samson See:
Novel real-time system design for floating-point sub-Nyquist multi-coset signal blind reconstruction. ISCAS 2015: 954-957 - [c42]Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang:
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). ISCAS 2015: 1913-1916 - [c41]Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang:
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. ISCAS 2015: 2589-2592 - 2014
- [j23]Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee:
Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing. Circuits Syst. Signal Process. 33(10): 3317-3329 (2014) - [j22]Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 989-1002 (2014) - [c40]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips. APCCAS 2014: 5-8 - [c39]Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho:
Synthesis of asynchronous QDI circuits using synchronous coding specifications. ISCAS 2014: 153-156 - [c38]Victor Adrian, Cui Keer, Bah-Hwee Gwee, Joseph Sylvester Chang:
A Randomized Modulation scheme for filterless digital Class D audio amplifiers. ISCAS 2014: 774-777 - [c37]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Ne Kyaw Zwa Lwin:
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. ISIC 2014: 320-323 - [c36]Salma Nashit, Victor Adrian, Cui Keer, Quoc-An Mai, Bah-Hwee Gwee, Joseph S. Chang:
A self-oscillating class D audio amplifier with dual voltage and current feedback. ISIC 2014: 480-483 - [c35]Tian-Shun Ng, Yin Sun, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang:
Design of an output stage for high switching frequency DC-DC converters. ISIC 2014: 488-491 - 2013
- [j21]Kok-Leong Chang, Joseph S. Chang, Bah-Hwee Gwee, Kwen-Siong Chong:
Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects. IEEE J. Emerg. Sel. Topics Circuits Syst. 3(1): 23-34 (2013) - [j20]Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee:
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks. IEEE J. Solid State Circuits 48(2): 573-586 (2013) - [c34]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. ISCAS 2013: 353-356 - [c33]Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. ISCAS 2013: 3022-3025 - [c32]Yiqiong Shi, Bah-Hwee Gwee:
Designing globally-asynchronous-locally-system from multi-rate Simulink model. NEWCAS 2013: 1-4 - 2012
- [j19]Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang:
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors. IEEE J. Solid State Circuits 47(3): 769-780 (2012) - [c31]Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang:
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. ISCAS 2012: 492-495 - [c30]Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A comparative study on asynchronous Quasi-Delay-Insensitive templates. ISCAS 2012: 1819-1822 - [c29]Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. ISCAS 2012: 1835-1838 - [c28]Yiqiong Shi, Bah-Hwee Gwee, Ye Ren, Thet Khaing Phone, Chan Wai Ting:
Extracting functional modules from flattened gate-level netlist. ISCIT 2012: 538-543 - 2011
- [j18]Yiqiong Shi, Bah-Hwee Gwee, Joseph Sylvester Chang:
Asynchronous DSP for low-power energy-efficient embedded systems. Microprocess. Microsystems 35(3): 318-328 (2011) - [j17]Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang:
Modeling and Synthesis of Asynchronous Pipelines. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 682-695 (2011) - [c27]Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A low-power dual-rail inputs write method for bit-interleaved memory cells. ISCAS 2011: 325-328 - [c26]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, Yin Sun, Kok-Leong Chang:
Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation. ISCAS 2011: 1936-1939 - 2010
- [j16]Victor Adrian, Joseph S. Chang, Bah-Hwee Gwee:
A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2320-2333 (2010) - [c25]Yiqiong Shi, Chan Wai Ting, Bah-Hwee Gwee, Ye Ren:
A highly efficient method for extracting FSMs from flattened gate-level netlist. ISCAS 2010: 2610-2613
2000 – 2009
- 2009
- [j15]Victor Adrian, Joseph S. Chang, Bah-Hwee Gwee:
A Low-Voltage Micropower Digital Class-D Amplifier Modulator for Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 337-349 (2009) - [j14]Bah-Hwee Gwee, Joseph S. Chang, Yiqiong Shi, Chien-Chung Chua, Kwen-Siong Chong:
A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(7): 1349-1359 (2009) - [c24]Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng:
A Performance Comparison on Asynchronous Matched-delay Templates. ISCAS 2009: 1008-1011 - [c23]Tong Lin, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic. ISCAS 2009: 3162-3165 - 2008
- [j13]Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang:
Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 985-998 (2008) - [c22]Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng:
A semi-custom memory design for an asynchronous 8051 microcontroller. ISCAS 2008: 3398-3401 - [c21]Kok-Leong Chang, Yao Zhu, Bah-Hwee Gwee:
De-synchronization of a point-of-sales digital-logic controller. ISCAS 2008: 3402-3405 - 2007
- [j12]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Design of several asynchronous-logic macrocells for a low-voltage micropower cell library. IET Circuits Devices Syst. 1(2): 161-169 (2007) - [j11]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low energy 16-bit Booth leapfrog array multiplier using dynamic adders. IET Circuits Devices Syst. 1(2): 170-174 (2007) - [j10]Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang:
Fast and memory-efficient invariant computation of ordinary Petri nets. IET Comput. Digit. Tech. 1(5): 612-624 (2007) - [j9]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors. IEEE J. Solid State Circuits 42(9): 2034-2045 (2007) - [c20]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A Low Energy FFT/IFFT Processor for Hearing Aids. ISCAS 2007: 1169-1172 - [c19]Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng:
An Asynchronous Dual-Rail Multiplier based on Energy-Efficient STFB Templates. ISCAS 2007: 3267-3270 - [c18]Kunal Mukherjee, Bah-Hwee Gwee:
A 32-point FFT based Noise Reduction Algorithm for Single Channel Speech Signals. ISCAS 2007: 3928-3931 - 2006
- [j8]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids. IEEE Trans. Circuits Syst. II Express Briefs 53-II(9): 853-857 (2006) - [c17]Chong-Fatt Law, Bah-Hwee Gwee, Joseph S. Chang:
Optimized Algorithm for Computing Invariants of Ordinary Petri Nets. ACIS-ICIS 2006: 23-28 - [c16]Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang:
An acoustic noise suppression system with reduced musical artifacts. ISCAS 2006 - [c15]Kok-Leong Chang, Bah-Hwee Gwee:
A low-energy low-voltage asynchronous 8051 microcontroller core. ISCAS 2006 - 2005
- [j7]Bah-Hwee Gwee, Meng-Hiot Lim:
An evolution search algorithm for solving N-queen problems. Int. J. Comput. Appl. Technol. 24(1): 43-48 (2005) - [j6]Bah-Hwee Gwee, Joseph Sylvester Chang, Victor Adrian:
A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(10): 2007-2022 (2005) - [j5]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A micropower low-voltage multiplier with reduced spurious switching. IEEE Trans. Very Large Scale Integr. Syst. 13(2): 255-265 (2005) - [c14]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low-voltage micropower multipliers with reduced spurious switching. ISCAS (4) 2005: 4078-4081 - [c13]Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang:
A combined interpolatorless interpolation and high accuracy sampling process for digital class D amplifiers. ISCAS (6) 2005: 5405-5408 - 2004
- [c12]Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang:
A novel combined first and second order Lagrange interpolation sampling process for a digital class D amplifier. ISCAS (3) 2004: 233-260 - [c11]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders. ISCAS (2) 2004: 437-440 - 2003
- [c10]Bah-Hwee Gwee, Joseph Sylvester Chang:
A Hybrid Genetic Hill-climbing Algorithm for Four-Coloring Map Problems. HIS 2003: 252-261 - [c9]Chien-Chung Chua, Bah-Hwee Gwee, Joseph Sylvester Chang:
A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter. ISCAS (5) 2003: 381-384 - [c8]Bah-Hwee Gwee, Joseph Sylvester Chang, Victor Adrian, H. Amir:
A novel sampling process and pulse generator for a low distortion digital pulse-width modulator for digital class D amplifiers. ISCAS (4) 2003: 504-507 - [c7]Khia-Ho Chang, Bah-Hwee Gwee, Joseph Sylvester Chang:
A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File. VLSI 2003: 166-172 - 2002
- [c6]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low-voltage micropower asynchronous multiplier for hearing instruments. ISCAS (1) 2002: 865-868 - [c5]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low-voltage asynchronous adders for low power and high speed applications. ISCAS (1) 2002: 873-876 - 2001
- [c4]Joseph Sylvester Chang, Bah-Hwee Gwee, Yong Seng Lon, Meng Tong Tan:
A novel low-power low-voltage Class D amplifier with feedback for improving THD, power efficiency and gain linearity. ISCAS (1) 2001: 635-638 - [c3]Huiyun Li, Bah-Hwee Gwee, Joseph Sylvester Chang:
A digital Class D amplifier design embodying a novel sampling process and pulse generator. ISCAS (4) 2001: 826-829 - 2000
- [j4]Bah-Hwee Gwee, Meng-Hiot Lim:
A GA with heuristic-based decoder for IC floorplanning. Integr. 28(2): 157-172 (2000) - [c2]Meng Tong Tan, Hock-Chuan Chua, Bah-Hwee Gwee, Joseph S. Chang:
An investigation on the parameters affecting total harmonic distortion in class D amplifiers. ISCAS 2000: 193-196
1990 – 1999
- 1996
- [j3]Bah-Hwee Gwee, M. H. Lim:
Polyominoes tiling by a genetic algorithm. Comput. Optim. Appl. 6(3): 273-291 (1996) - [j2]M. H. Lim, Susanto Rahardja, Bah-Hwee Gwee:
A GA paradigm for learning fuzzy rules. Fuzzy Sets Syst. 82(2): 177-186 (1996) - 1993
- [j1]M. H. Lim, Bah-Hwee Gwee, Y. Kawada:
Intelligent monitoring of a frequency-trimming process. J. Intell. Manuf. 4(6): 375-383 (1993) - [c1]Bah-Hwee Gwee, Meng-Hiot Lim, Jiun-Sien Ho:
Solving four-colouring map problem using genetic algorithm. ANNES 1993: 332-333
Coauthor Index
Joseph Sylvester Chang
aka: Joseph S. Chang
aka: Joseph S. Chang
[c77] [j36] [c73] [c72] [c71] [j35] [c69] [c65] [c62] [c60] [j28] [j26] [j25] [c55] [c53] [c50] [c48] [c46] [j24] [c42] [c41] [j22] [c40] [c39] [c38] [c37] [c36] [c35] [j21] [j20] [c34] [c33] [j19] [c31] [c30] [c29] [j18] [j17] [c27] [c26] [j16] [j15] [j14] [c23] [j13] [j12] [j11] [j10] [j9] [c20] [j8] [c17] [c16] [j6] [j5] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2]
[j40] [c84] [c76] [j36] [c74] [c73] [c72] [j35] [j34] [j33] [c69] [c68] [c66] [c65] [c64] [c63] [j31] [j30] [j29] [c62] [c60] [c59] [j26] [c58] [j25] [c56] [c54] [c52] [c51] [c50] [c49] [c48] [c47] [c45] [c44] [j24] [c42] [c41] [j23] [j22] [c40] [c39] [c37] [j21] [j20] [c34] [c33] [j19] [c31] [c30] [c29] [c27] [c26] [j14] [c23] [j12] [j11] [j9] [c20] [j8] [j5] [c14] [c11] [c6] [c5]
Ne Kyaw Zwa Lwin
aka: Kyaw Zwa Lwin Ne
aka: Kyaw Zwa Lwin Ne
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