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ORCIDBalaji Vaidyanathan
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2000 – 2009
- 2009
[c8]Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie:
Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning. ICCAD 2009: 164-171- [c7]Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie, Yu Wang
:
NBTI-aware statistical circuit delay assessment. ISQED 2009: 13-18 - 2007
- [c6]Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy, Rajaraman Ramanarayanan, Balaji Vaidyanathan:
A Process Scheduler-Based Approach to NoC Power Management. VLSI Design 2007: 77-82 - [c5]Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Architecting Microprocessor Components in 3D Design Space. VLSI Design 2007: 103-108 - [c4]Feng Wang, Yuan Xie, R. Rajaraman, Balaji Vaidyanathan:
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. VLSI Design 2007: 165-170 - [c3]Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk, Rajaraman Ramanarayanan, Balaji Vaidyanathan:
Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors. VLSI Design 2007: 251-258 - 2006
- [c2]Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan, Rong Luo:
Leakage Optimized DECAP Design for FPGAs. APCCAS 2006: 960-963 - [c1]Balaji Vaidyanathan, Yuan Xie:
Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression. SoCC 2006: 193-196
Coauthor Index
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